clk.vhd

EDA课程设计

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED;
entity CLK is
port(clk0,clr,clr1,mclock,hoclock,tm,th,res,rst:in std_logic;
    out1,out2,out3,out4,out5,out6:out std_logic_vector(3 downto 0);
    speaker:out std_logic
    );
end CLK;

ARCHITECTURE Behavioral OF CLK IS
SIGNAL sech,secl:std_logic_vector(3 downto 0);
SIGNAL minh,minl:std_logic_vector(3 downto 0);
SIGNAL hh,hl:std_logic_vector(3 downto 0);
SIGNAL hoh,hol,mh,ml:STD_LOGIC_VECTOR(3 DOWNTO 0);
signal clk:std_logic_vector(8 downto 0);
signal clkl:std_logic_vector(1 downto 0);
SIGNAL thh,thl,tmh,tml:STD_LOGIC_VECTOR(3 DOWNTO 0);
signal clk1,q500,qlk,clk500,speaker1,music,a,b,c:std_logic;
begin

process(clk0)
begin
if (clk0'event and clk0='1') then
   if clkl="10" then 
      clkl<="00";
   else clkl<=clkl+1;
clk500<=clkl(1);
   end if;
   if clk="111110100" then
      clk<="000000000";
   else clk<=clk+1;
end if;
clk1<=clk(8);
end if;
end process;

process(clk1,clr)
begin
if clr='1' then
   sech<="0000";
   secl<="0000";
elsif clk1'event and clk1='1' then
   if sech="0101" and secl="1000" then
      secl<="1001";
   elsif secl<"1001" then
      secl<=secl+1;
   else
      secl<="0000";

      if sech<"0101" then
         sech<=sech+1;
      else
         sech<="0000";
      end if;
   end if;
end if;
end process;


process(clk1,clr,sech,secl,rst)
begin
if clr='1' then
   minh<="0000";
   minl<="0000";
elsif rst='1' then
      minh<=tmh;
      minl<=tml;
elsif clk1'event and clk1='1' then
      if ((sech="0101")AND(secl="1001")) then
         if minh="0101" and minl="1000" then
            minl<="1001";
         elsif minl<"1001" then
               minl<=minl+1;
         else
               minl<="0000";

               if minh<"0101" then
                  minh<=minh+1;
               else
                  minh<="0000";
               end if;
         end if;
      end if;
end if;
end process;


process(clk1,clr,sech,secl,minh,minl,rst)
begin
if clr='1' then
   hh<="0000";
   hl<="0000";
elsif rst='1' then
hh<=thh;
hl<=thl;
elsif clk1'event and clk1='1' then
      IF((sech="0101")AND(secl="1001")AND(minh="0101")AND(minl="1001")) then
        if hh="0010" and hl="0011" then
           hh<="0000";
           hl<="0000";
         elsif hl<"1001" then
               hl<=hl+1;
elsif hl ="1001" then
                   hh<= hh+1;
                  hl<="0000";
         end if;
      end if;
end if;
end process;

process(clk1,minh,minl,sech,secl)
  begin
if clk1'event and clk1='1' then
   if minh="0101" and minl="1001" and sech="0101" then
      if secl="0001" or secl="0011" or secl="0101" or secl="0111" then
         q500<='1';
      else
         q500<='0';
      end if;
   end if;
   if minh="0101" and minl="1001" and sech="0101" and secl="1001" then
      qlk<='1';
   else
      qlk<='0';
   end if;
end if;
a<=qlk and clk500;
b<=q500 and clk0;
speaker1<=a or b;
 end process;

process(clr1,tm)
begin
if clr1='1' then
   tmh<="0000";
   tml<="0000";
elsif tm'event and tm='1' then
   if tmh="0101" and tml="1000" then
      tml<="1001";
   elsif tml<"1001" then
      tml<=tml+1;
   else
      tml<="0000";

      if tmh<"0101" then
         tmh<=tmh+1;
      else
         tmh<="0000";
      end if;
   end if;
end if;
end process;

process(clr1,th)
begin   
if clr1='1' then
   thh<="0000";
   thl<="0000";
elsif th'event and th='1' then 
		if thh="0010" and thl="0011" then
           thh<="0000";
           thl<="0000";
         elsif thl<"1001" then
               thl<=hl+1;
elsif thl ="1001" then
thh<= thh+1;
thl<="0000";
         end if;
	END IF;
END PROCESS;


process(clr1,mclock)
begin
if clr1='1' then
   mh<="0000";
   ml<="0000";
elsif mclock'event and mclock='1' then
   if mh="0101" and ml="1000" then
      ml<="1001";
   elsif ml<"1001" then
      ml<=ml+1;
   else
      ml<="0000";

      if mh<"0101" then
         mh<=mh+1;
      else
         mh<="0000";
      end if;
   end if;
end if;
end process;
process(clr1,hoclock)
begin   
if clr1='1' then
   hoh<="0000";
   hol<="0000";
elsif hoclock'event and hoclock='1' then 
		if hoh="0010" and hol="0011" then
           hoh<="0000";
           hol<="0000";
         elsif hol<"1001" then
               hol<=hol+1;
elsif hol ="1001" then
hoh<= hoh+1;
hol<="0000";
        end if;
	END IF;
END PROCESS;

process(hoh,hol,mh,ml,hh,hl,minh,minl,res)
begin
   if res='0'  then
IF(( hoh= hh)AND(hol = hl)AND(mh = minh )AND(ml = minl)) THEN
music<='1';
else
music<='0';
end if;
else music<='0';
end if;
c<=music and clk0;
speaker<=speaker1 or c;
end process;


PROCESS(mclock,hoclock)
BEGIN
IF ( mclock='1' or hoclock='1') THEN
    out1<=hoh;
    out2<=hol;
    out3<=mh;
    out4<=ml;
    out5<="0000";
    out6<="0000";
ELSE	
    out1<=hh;
    out2<=hl;
    out3<=minh;
    out4<=minl;
    out5<=sech;
    out6<=secl;
end if;
end process;
end Behavioral;