generator.vhd

伪随机序列码发生器及基带传输CMI码编、译码的VHDL语言实现

--伪随机序列发生器
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY GENERATOR IS
  PORT(clk:IN STD_LOGIC;
       load:IN STD_LOGIC;
       Q:OUT STD_LOGIC);
END GENERATOR;

ARCHITECTURE RTL OF GENERATOR IS
  SIGNAL Q0,Q1,Q2:STD_LOGIC;
  BEGIN
  PROCESS(clk,load)
    BEGIN
    IF(clk'EVENT AND clk='1') THEN
      IF(load='1') THEN
        Q0<='1';
        Q1<='1';
        Q2<='1';
        Q<=Q0;
      ELSE
        Q0<=Q1;
        Q1<=Q2;
        Q2<=Q1 XOR Q0;
        Q<=Q0;
      END IF;
    END IF;
  END PROCESS;
END RTL;