📄 cmi_coder_decoder.rpt
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Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\vhdl\cmi_coder_decoder.rpt
cmi_coder_decoder
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 8 - B 03 DFFE + 0 2 0 1 |CMI_CODER:11|:3
- 7 - B 03 DFFE + 0 2 0 1 |CMI_CODER:11|:5
- 2 - B 03 DFFE + 0 1 0 2 |CMI_CODER:11|sig (|CMI_CODER:11|:7)
- 1 - B 03 DFFE + 0 2 1 0 |CMI_DECODER:12|:4
- 5 - B 03 DFFE + 0 1 1 3 |GENERATOR:3|:3
- 6 - B 03 DFFE + 1 1 0 2 |GENERATOR:3|Q0 (|GENERATOR:3|:5)
- 4 - B 03 DFFE + 1 1 0 2 |GENERATOR:3|Q1 (|GENERATOR:3|:6)
- 3 - B 03 DFFE + 1 2 0 1 |GENERATOR:3|Q2 (|GENERATOR:3|:7)
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: e:\vhdl\cmi_coder_decoder.rpt
cmi_coder_decoder
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 1/ 96( 1%) 1/ 48( 2%) 0/ 48( 0%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
D: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
E: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\vhdl\cmi_coder_decoder.rpt
cmi_coder_decoder
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 8 clk
Device-Specific Information: e:\vhdl\cmi_coder_decoder.rpt
cmi_coder_decoder
** EQUATIONS **
clk : INPUT;
LOAD : INPUT;
-- Node name is 'deco_out'
-- Equation name is 'deco_out', type is output
deco_out = _LC1_B3;
-- Node name is 'Q'
-- Equation name is 'Q', type is output
Q = _LC5_B3;
-- Node name is '|CMI_CODER:11|:7' = '|CMI_CODER:11|sig'
-- Equation name is '_LC2_B3', type is buried
_LC2_B3 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = !_LC2_B3 & _LC5_B3
# _LC2_B3 & !_LC5_B3;
-- Node name is '|CMI_CODER:11|:3'
-- Equation name is '_LC8_B3', type is buried
_LC8_B3 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = !_LC2_B3 & _LC5_B3;
-- Node name is '|CMI_CODER:11|:5'
-- Equation name is '_LC7_B3', type is buried
_LC7_B3 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = !_LC2_B3
# !_LC5_B3;
-- Node name is '|CMI_DECODER:12|:4'
-- Equation name is '_LC1_B3', type is buried
_LC1_B3 = DFFE( _EQ004, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = !_LC7_B3 & !_LC8_B3
# _LC7_B3 & _LC8_B3;
-- Node name is '|GENERATOR:3|:5' = '|GENERATOR:3|Q0'
-- Equation name is '_LC6_B3', type is buried
_LC6_B3 = DFFE( _EQ005, GLOBAL( clk), VCC, VCC, VCC);
_EQ005 = _LC4_B3
# LOAD;
-- Node name is '|GENERATOR:3|:6' = '|GENERATOR:3|Q1'
-- Equation name is '_LC4_B3', type is buried
_LC4_B3 = DFFE( _EQ006, GLOBAL( clk), VCC, VCC, VCC);
_EQ006 = _LC3_B3
# LOAD;
-- Node name is '|GENERATOR:3|:7' = '|GENERATOR:3|Q2'
-- Equation name is '_LC3_B3', type is buried
_LC3_B3 = DFFE( _EQ007, GLOBAL( clk), VCC, VCC, VCC);
_EQ007 = !_LC4_B3 & _LC6_B3
# _LC4_B3 & !_LC6_B3
# LOAD;
-- Node name is '|GENERATOR:3|:3'
-- Equation name is '_LC5_B3', type is buried
_LC5_B3 = DFFE( _LC6_B3, GLOBAL( clk), VCC, VCC, VCC);
Project Information e:\vhdl\cmi_coder_decoder.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 18,354K
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