reg_file.sim

6端口寄存器IP内核VHDL源代码

; 
; MTI script for analysis of
;   reg_file_32_8_6port
; into register_file library
; 
; set reg_file_vhdl R:\webs\model_9807
; set reg_file_tools R:\webs\model_9807
;
; set vfp_vhdl R:\webs\model_9807
; set vfp_tools R:\webs\model_9807

; do $vfp_tools/vfp.cmp
; do $reg_file_tools/reg_file.cmp
; do $reg_file_tools/reg_file.sim

vsim -t ns -lib register_file reg_file_32_8_6port_tb modular
wave /write_sig
wave /address_write
wave /data_in
wave /simulation_time
wave /read_sig
wave /address_read
wave /data_out
wave /dut/addr_WR
wave /dut/WE_WR
wave /dut/data_WR
wave /dut/data_WR_select
wave /dut/latch_array_in
wave /dut/en
wave /dut/latch_array_out
wave /dut/addr_RD