reg_file_32_8_6port.dec

6端口寄存器IP内核VHDL源代码

library IEEE;
library vfp;
  use IEEE.std_logic_1164.all;
  use vfp.hardware_specifications.all;

package reg_file_32_8_6port_cmpt is

  component reg_file_32_8_6port is
  generic (
    num_write_ports : integer := 1;
    num_read_ports  : integer := 1;
    -- depth : integer := 32;
    -- data_width : integer := 8;
    num_bidirectional_ports : integer := 0
  );
  port (
    write    : in std_ulogic_vector(((num_write_ports-1) + num_bidirectional_ports) downto 0);
    read     : in std_ulogic_vector((( num_read_ports-1) + num_bidirectional_ports) downto 0);
    address_write : in std_ulogic_2D_array(2 downto 0, 4 downto 0);
    address_read  : in std_ulogic_2D_array(2 downto 0, 4 downto 0);
    data_in  : in  std_ulogic_2D_array(2 downto 0, 7 downto 0);
    data_out : out std_ulogic_2D_array(2 downto 0, 7 downto 0)
  );
  end component;

end reg_file_32_8_6port_cmpt;