sdram_inf.vhd

sdram操作的vhdl源代码

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity sdram_inf is port(
clk,rst,iosel : in std_logic;
ad   : inout std_logic_vector(31 downto 0);
dq   : out std_logic_vector(15 downto 0);
data_rd_out,data_wr : in std_logic;
ext_add : in std_logic_vector(7 downto 0);
int_fifo_empty,int_fifo_full : in std_logic;
int_fifo_rd,int_fifo_wr,int_fifo_rden : buffer std_logic;
sd_cs,sd_ras,sd_cas,sd_we,sd_dqm : out std_logic;
sd_clk : buffer std_logic;
sd_add : out std_logic_vector(11 downto 0);
sd_ba  : out std_logic_vector(1 downto 0));
end sdram_inf;
architecture beha of sdram_inf is 
type sdram_state is (idle,wr_st1,wr_st2,wr_st3,act_st,wait1,cas_st,
                     rd_st1,rd_st2,wait2,wait3,wait4,sp_st,ref_st);
signal pre_state,nxt_state : sdram_state;
signal sdram_ctl_sel,ref_req,datamsk : std_logic;
signal sdram_ctl_reg : std_logic_vector(7 downto 0);
signal sdram_wradd_reg,sdram_rdadd_reg : std_logic_vector(21 downto 0);
signal sdram_wradd_sel,sdram_rdadd_sel : std_logic;
signal wr1sel,wr2sel,wr3sel,wr4sel,rd1sel,rd2sel,rd3sel,rd4sel : std_logic;
signal ref_counter : std_logic_vector(7 downto 0);
signal intfiford,intfifowr,intfiforden : std_logic;
signal sdcs,sdras,sdcas,sdwe,sddqm,ref_clr,mode_clr : std_logic;
signal sdba : std_logic_vector(1 downto 0);
signal sdadd : std_logic_vector(11 downto 0);
begin 
  con_pro : process(clk,rst)
      begin if iosel='1' and ext_add="10100000" then sdram_ctl_sel<='1';
                                  else sdram_ctl_sel<='0';
            end if;
            if iosel='1' and ext_add="10100100" then sdram_wradd_sel<='1';
                                  else sdram_wradd_sel<='0';
            end if;
            if iosel='1' and ext_add="10101000" then sdram_rdadd_sel<='1';
                                  else sdram_rdadd_sel<='0';
            end if;
            if rst='0' then sdram_wradd_reg<=(others=>'0');
               elsif rising_edge(clk) then if (data_wr='1' and sdram_wradd_sel='1' ) then 
                     sdram_wradd_reg<=ad(21 downto 0);
                     elsif wr1sel='1' then 
                       sdram_wradd_reg(21 downto 2)<=sdram_wradd_reg(21 downto 2)+1;
                     end if;
            end if;
            if rst='0' then sdram_rdadd_reg<=(others=>'0');
               elsif rising_edge(clk) then if (data_wr='1' and sdram_rdadd_sel='1' ) then 
                     sdram_rdadd_reg<=ad(21 downto 0);
                     elsif rd1sel='1' then 
                       sdram_rdadd_reg(21 downto 2)<=sdram_rdadd_reg(21 downto 2)+1;
                     end if;
            end if;
            if rst='0' then sdram_ctl_reg<=(others=>'0');
            elsif mode_clr='1' then sdram_ctl_reg(3 downto 0)<="0000";
                       elsif rising_edge(clk) then if (data_wr='1' and sdram_ctl_sel='1') then 
                              sdram_ctl_reg<=ad(7 downto 0);
                             end if;
            end if;
            if rst='0' then ref_counter<=(others=>'0');
            elsif rising_edge(clk) then ref_counter<=ref_counter+1;
            end if;
            if rst='0' or ref_clr='1' then ref_req<='0';
            elsif rising_edge(clk) then if ref_counter="11111111" or sdram_ctl_reg(1)='1' then 
                                     ref_req<='1';
                                     end if;
            end if;
            if rising_edge(clk) then if pre_state=ref_st then 
                         ref_clr<='1';
                    else ref_clr<='0';
                             end if;
            end if;    
            if rising_edge(clk) then if pre_state=sp_st then 
                         mode_clr<='1';
                     else mode_clr<='0';
                     end if;
            end if;
            case pre_state is 
            when idle => if (sdram_ctl_reg(1)='1' or ref_req='1') then 
                          nxt_state<=ref_st;
                    elsif (sdram_ctl_reg(2)='1' or sdram_ctl_reg(3)='1') then 
                          nxt_state<=sp_st;
                    elsif (sdram_ctl_reg(4)='1' and int_fifo_empty='0') then 
                          nxt_state<=wr_st1;
                    elsif (sdram_ctl_reg(5)='1' and int_fifo_full='0') then 
                          nxt_state<=act_st;
                    else nxt_state<=idle;
                    end if;
            when ref_st => nxt_state<=wait2;
            when sp_st  => nxt_state<=wait2;
            when wr_st1 => nxt_state<=wr_st2;
            when wr_st2 => nxt_state<=wr_st3;
            when wr_st3 => nxt_state<=act_st;
            when act_st => nxt_state<=wait1;
            when wait1 =>  nxt_state<=cas_st;
            when cas_st => if sdram_ctl_reg(4)='1' then nxt_state<=wait2;
                      elsif sdram_ctl_reg(5)='1' then nxt_state<=rd_st1;
                      else  nxt_state<=idle;
                      end if;
            when rd_st1 => if int_fifo_full='1' then nxt_state<=idle;
                           else nxt_state<=rd_st2;
                      end if;
            when rd_st2 => nxt_state<=wait2;
            when wait2  => nxt_state<=wait3;
            when wait3  => nxt_state<=wait4;
            when wait4  => nxt_state<=idle;
            when others => nxt_state<=idle;
            end case;
            if rst='0' then wr1sel<='0';wr2sel<='0';wr3sel<='0';wr4sel<='0';
            elsif rising_edge(clk) then if pre_state=wait1 and sdram_ctl_reg(4)='1' then 
                     wr1sel<='1';
                     else wr1sel<='0';
                     end if;
                     wr2sel<=wr1sel;
                     wr3sel<=wr2sel;
                     wr4sel<=wr3sel;
             end if;
             if rst='0' then rd1sel<='0';rd2sel<='0';rd3sel<='0';rd4sel<='0';
             elsif rising_edge(clk) then if pre_state=rd_st2  then 
                     rd1sel<='1';
                     else rd1sel<='0';
                     end if;
                     rd2sel<=rd1sel;
                     rd3sel<=rd2sel;
                     rd4sel<=rd3sel;
              end if;                 
         datamsk<=rd1sel or rd2sel or rd3sel or rd4sel or wr1sel or wr2sel or wr3sel or wr4sel;
         if rst='0' then sd_cs<='1';sd_ras<='1';sd_cas<='1';sd_we<='1';sd_dqm<='1';
         elsif rising_edge(clk) then 
               sd_cs<=sdcs;
               sd_ras<=sdras;
               sd_cas<=sdcas;
               sd_we<=sdwe;
               sd_dqm<=sddqm;
               sd_ba<=sdba;
               sd_add<=sdadd;
         end if;
               sd_clk<=clk;
         if rst='0' then --int_fifo_rd<='0';
                         int_fifo_rden<='0';
                         --int_fifo_wr<='0';
         elsif rising_edge(clk) then 
--               int_fifo_rd<=intfiford;
               int_fifo_rden<=intfiforden;
--               int_fifo_wr<=intfifowr;
         end if;
         end process;
  state_pro : process(clk,rst)
         begin if rst='0' then pre_state<=idle;
               elsif rising_edge(clk) then pre_state<=nxt_state;
               end if;
         end process;
         sdcs<='0' when pre_state=ref_st or pre_state=sp_st or 
                        pre_state=act_st or pre_state=cas_st 
                   else '1';
         sdras<='0' when pre_state=ref_st or pre_state=sp_st or 
                         pre_state=act_st 
                    else '1';
         sdcas<='0' when pre_state=ref_st or (pre_state=sp_st and sdram_ctl_reg(3)='1') or 
                         pre_state=cas_st
                    else '1';
         sdwe<='0'  when pre_state=sp_st or (pre_state=cas_st and sdram_ctl_reg(4)='1')
                    else '1';
         sddqm<='0' when pre_state=wait1 or pre_state=cas_st or pre_state=rd_st1 or pre_state=rd_st2 or datamsk='1'
                    else '1';
         sdba<=sdram_rdadd_reg(21 downto 20) when (pre_state=act_st or pre_state=cas_st) and sdram_ctl_reg(5)='1'
               else sdram_wradd_reg(21 downto 20) when (pre_state=act_st or pre_state= cas_st) and sdram_ctl_reg(4)='1'
               else "00";
         sdadd(7 downto 0)<=sdram_rdadd_reg(7 downto 0) when pre_state=cas_st and sdram_ctl_reg(5)='1'
                       else sdram_wradd_reg(7 downto 0) when pre_state=cas_st and sdram_ctl_reg(4)='1'
                       else sdram_rdadd_reg(15 downto 8) when pre_state=act_st and sdram_ctl_reg(5)='1'
                       else sdram_wradd_reg(15 downto 8) when pre_state=act_st and sdram_ctl_reg(4)='1'
                       else "00110010" when pre_state=sp_st and sdram_ctl_reg(3)='1'
                       else "00000000";
        sdadd(11 downto 8)<=sdram_rdadd_reg(19 downto 16) when pre_state=act_st and sdram_ctl_reg(5)='1'
                       else sdram_wradd_reg(19 downto 16) when pre_state=act_st and sdram_ctl_reg(4)='1'
                       else "0100" when pre_state=cas_st or (pre_state=sp_st and sdram_ctl_reg(2)='1')
                       else "0000"; 
        int_fifo_rd<=wr1sel or wr2sel or wr3sel or wr4sel;
        intfiforden<='1' when (pre_state=wait1 and sdram_ctl_reg(4)='1') or int_fifo_rd='1'
                    else '0';
        int_fifo_wr<=rd1sel or rd2sel or rd3sel or rd4sel;
   --     intfifowr<=rd1sel or rd2sel or rd3sel or rd4sel;
        ad(21 downto 0)<=sdram_rdadd_reg when data_rd_out='1' and sdram_rdadd_sel='1'
               else sdram_wradd_reg when data_rd_out='1' and sdram_wradd_sel='1'
               else "ZZZZZZZZZZZZZZZZZZZZZZ";
        ad(31 downto 22)<="0000000000" when data_rd_out='1' and sdram_rdadd_sel='1'
               else "0000000000" when data_rd_out='1' and sdram_wradd_sel='1'
               else "ZZZZZZZZZZ";
        dq<="0000000000000000" when int_fifo_wr='1'
            else "ZZZZZZZZZZZZZZZZ";
        end beha;