one.tan.rpt

用VHDL写成的一个数控分频程序.本例中把64HZ分成1HZ

; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[1] ; num[5]  ; clk        ; clk      ; None                        ; None                      ; 2.192 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[1] ; num[6]  ; clk        ; clk      ; None                        ; None                      ; 2.192 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[1] ; num[4]  ; clk        ; clk      ; None                        ; None                      ; 2.192 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[0] ; num[3]  ; clk        ; clk      ; None                        ; None                      ; 2.054 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[1] ; num[3]  ; clk        ; clk      ; None                        ; None                      ; 1.975 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[0] ; num[2]  ; clk        ; clk      ; None                        ; None                      ; 1.974 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[2] ; num[5]  ; clk        ; clk      ; None                        ; None                      ; 1.946 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[2] ; num[6]  ; clk        ; clk      ; None                        ; None                      ; 1.946 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[2] ; num[4]  ; clk        ; clk      ; None                        ; None                      ; 1.946 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[3] ; num[5]  ; clk        ; clk      ; None                        ; None                      ; 1.920 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[3] ; num[6]  ; clk        ; clk      ; None                        ; None                      ; 1.920 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[3] ; num[4]  ; clk        ; clk      ; None                        ; None                      ; 1.920 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[5] ; num[6]  ; clk        ; clk      ; None                        ; None                      ; 1.903 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[1] ; num[2]  ; clk        ; clk      ; None                        ; None                      ; 1.895 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[0] ; num[1]  ; clk        ; clk      ; None                        ; None                      ; 1.894 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[4] ; num[6]  ; clk        ; clk      ; None                        ; None                      ; 1.804 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[2] ; num[3]  ; clk        ; clk      ; None                        ; None                      ; 1.725 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[4] ; num[5]  ; clk        ; clk      ; None                        ; None                      ; 1.724 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[5] ; num[5]  ; clk        ; clk      ; None                        ; None                      ; 1.279 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[6] ; num[6]  ; clk        ; clk      ; None                        ; None                      ; 1.278 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[1] ; num[1]  ; clk        ; clk      ; None                        ; None                      ; 1.271 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[0] ; num[0]  ; clk        ; clk      ; None                        ; None                      ; 1.270 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[2] ; num[2]  ; clk        ; clk      ; None                        ; None                      ; 1.113 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[4] ; num[4]  ; clk        ; clk      ; None                        ; None                      ; 1.112 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[3] ; num[3]  ; clk        ; clk      ; None                        ; None                      ; 1.105 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[6] ; t1~reg0 ; clk        ; clk      ; None                        ; None                      ; 1.034 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[5] ; t1~reg0 ; clk        ; clk      ; None                        ; None                      ; 0.845 ns                ;
+-------+------------------------------------------------+--------+---------+------------+----------+-----------------------------+---------------------------+-------------------------+


+---------------------------------------------------------------+
; tco                                                           ;
+-------+--------------+------------+---------+----+------------+
; Slack ; Required tco ; Actual tco ; From    ; To ; From Clock ;
+-------+--------------+------------+---------+----+------------+
; N/A   ; None         ; 6.446 ns   ; t1~reg0 ; t1 ; clk        ;
+-------+--------------+------------+---------+----+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Mon Dec 31 21:12:59 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off one -c one --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 275.03 MHz between source register "num[0]" and destination register "num[5]"
    Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 2.269 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y18_N1; Fanout = 3; REG Node = 'num[0]'
            Info: 2: + IC(0.532 ns) + CELL(0.564 ns) = 1.096 ns; Loc. = LC_X1_Y18_N1; Fanout = 2; COMB Node = 'num[0]~62'
            Info: 3: + IC(0.000 ns) + CELL(0.078 ns) = 1.174 ns; Loc. = LC_X1_Y18_N2; Fanout = 2; COMB Node = 'num[1]~61'
            Info: 4: + IC(0.000 ns) + CELL(0.078 ns) = 1.252 ns; Loc. = LC_X1_Y18_N3; Fanout = 2; COMB Node = 'num[2]~60'
            Info: 5: + IC(0.000 ns) + CELL(0.178 ns) = 1.430 ns; Loc. = LC_X1_Y18_N4; Fanout = 3; COMB Node = 'num[3]~59'
            Info: 6: + IC(0.000 ns) + CELL(0.839 ns) = 2.269 ns; Loc. = LC_X1_Y18_N6; Fanout = 4; REG Node = 'num[5]'
            Info: Total cell delay = 1.737 ns ( 76.55 % )
            Info: Total interconnect delay = 0.532 ns ( 23.45 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 2.954 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 8; CLK Node = 'clk'
                Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X1_Y18_N6; Fanout = 4; REG Node = 'num[5]'
                Info: Total cell delay = 2.180 ns ( 73.80 % )
                Info: Total interconnect delay = 0.774 ns ( 26.20 % )
            Info: - Longest clock path from clock "clk" to source register is 2.954 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 8; CLK Node = 'clk'
                Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X1_Y18_N1; Fanout = 3; REG Node = 'num[0]'
                Info: Total cell delay = 2.180 ns ( 73.80 % )
                Info: Total interconnect delay = 0.774 ns ( 26.20 % )
        Info: + Micro clock to output delay of source is 0.224 ns
        Info: + Micro setup delay of destination is 0.037 ns
Info: tco from clock "clk" to destination pin "t1" through register "t1~reg0" is 6.446 ns
    Info: + Longest clock path from clock "clk" to source register is 2.954 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 8; CLK Node = 'clk'
        Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X1_Y18_N8; Fanout = 1; REG Node = 't1~reg0'
        Info: Total cell delay = 2.180 ns ( 73.80 % )
        Info: Total interconnect delay = 0.774 ns ( 26.20 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 3.268 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y18_N8; Fanout = 1; REG Node = 't1~reg0'
        Info: 2: + IC(1.144 ns) + CELL(2.124 ns) = 3.268 ns; Loc. = PIN_7; Fanout = 0; PIN Node = 't1'
        Info: Total cell delay = 2.124 ns ( 64.99 % )
        Info: Total interconnect delay = 1.144 ns ( 35.01 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Mon Dec 31 21:13:00 2007
    Info: Elapsed time: 00:00:01