one.vhd

来自「用VHDL写成的一个数控分频程序.本例中把64HZ分成1HZ」· VHDL 代码 · 共 24 行

library ieee;                      
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity one is
 port (clk:in std_logic;             --64hz的时针频率;
       t1:out std_logic 
       );
end entity one;
architecture one of one is
signal num: integer range 64 downto 0:=0;
begin 
  process(clk)
--variable num:integer range 65 downto 0:=0;
begin
if clk'event and clk='1' then
   if(num<32)then  num<=num+1;t1<='1' ;
   elsif(num>=32)  then num<=num+1; t1<='0';
end if;
end if;
--if(num=64) then t1<='1';num:=0;
--else t1<='0';
--end if ;
end process;
end;