dds_vhdl.map.summary

来自「rom地址宽度8位」· SUMMARY 代码 · 共 9 行

Analysis & Synthesis Status : Successful - Fri Dec 28 17:35:17 2007
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Full Version
Revision Name : DDS_VHDL
Top-level Entity Name : DDS_VHDL
Family : FLEX10K
Total logic elements : 64
Total pins : 28
Total memory bits : 4,096