dds_vhdl.tan.qmsg

来自「rom地址宽度8位」· QMSG 代码 · 共 10 行 · 第 1/5 页

{ "Info" "ITDB_TSU_RESULT" "REG8B:u5\|DOUT\[7\] PWORD\[4\] CLK 10.100 ns register " "Info: tsu for register \"REG8B:u5\|DOUT\[7\]\" (data pin = \"PWORD\[4\]\", clock pin = \"CLK\") is 10.100 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "12.900 ns + Longest pin register " "Info: + Longest pin to register delay is 12.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.500 ns) 3.500 ns PWORD\[4\] 1 PIN PIN_19 2 " "Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_19; Fanout = 2; PIN Node = 'PWORD\[4\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { PWORD[4] } "NODE_NAME" } } { "DDS_VHDL.vhd" "" { Text "D:/source/Quartus/backup/DDS_2/DDS_VHDL.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.900 ns) + CELL(1.200 ns) 7.600 ns ADDER8B:u4\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[4\] 2 COMB LC5_B5 2 " "Info: 2: + IC(2.900 ns) + CELL(1.200 ns) = 7.600 ns; Loc. = LC5_B5; Fanout = 2; COMB Node = 'ADDER8B:u4\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[4\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.100 ns" { PWORD[4] ADDER8B:u4|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[4] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 7.900 ns ADDER8B:u4\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[5\] 3 COMB LC6_B5 2 " "Info: 3: + IC(0.000 ns) + CELL(0.300 ns) = 7.900 ns; Loc. = LC6_B5; Fanout = 2; COMB Node = 'ADDER8B:u4\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[5\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.300 ns" { ADDER8B:u4|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[4] ADDER8B:u4|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[5] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 8.200 ns ADDER8B:u4\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[6\] 4 COMB LC7_B5 1 " "Info: 4: + IC(0.000 ns) + CELL(0.300 ns) = 8.200 ns; Loc. = LC7_B5; Fanout = 1; COMB Node = 'ADDER8B:u4\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[6\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.300 ns" { ADDER8B:u4|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[5] ADDER8B:u4|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[6] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 9.500 ns ADDER8B:u4\|lpm_add_sub:Add0\|addcore:adder\|unreg_res_node\[7\] 5 COMB LC8_B5 1 " "Info: 5: + IC(0.000 ns) + CELL(1.300 ns) = 9.500 ns; Loc. = LC8_B5; Fanout = 1; COMB Node = 'ADDER8B:u4\|lpm_add_sub:Add0\|addcore:adder\|unreg_res_node\[7\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.300 ns" { ADDER8B:u4|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[6] ADDER8B:u4|lpm_add_sub:Add0|addcore:adder|unreg_res_node[7] } "NODE_NAME" } } { "addcore.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/addcore.tdf" 95 16 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(1.200 ns) 12.900 ns REG8B:u5\|DOUT\[7\] 6 REG LC1_B2 8 " "Info: 6: + IC(2.200 ns) + CELL(1.200 ns) = 12.900 ns; Loc. = LC1_B2; Fanout = 8; REG Node = 'REG8B:u5\|DOUT\[7\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.400 ns" { ADDER8B:u4|lpm_add_sub:Add0|addcore:adder|unreg_res_node[7] REG8B:u5|DOUT[7] } "NODE_NAME" } } { "REG8B.vhd" "" { Text "D:/source/Quartus/backup/DDS_2/REG8B.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.800 ns ( 60.47 % ) " "Info: Total cell delay = 7.800 ns ( 60.47 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.100 ns ( 39.53 % ) " "Info: Total interconnect delay = 5.100 ns ( 39.53 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.900 ns" { PWORD[4] ADDER8B:u4|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[4] ADDER8B:u4|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[5] ADDER8B:u4|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[6] ADDER8B:u4|lpm_add_sub:Add0|addcore:adder|unreg_res_node[7] REG8B:u5|DOUT[7] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "12.900 ns" { PWORD[4] PWORD[4]~out ADDER8B:u4|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[4] ADDER8B:u4|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[5] ADDER8B:u4|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[6] ADDER8B:u4|lpm_add_sub:Add0|addcore:adder|unreg_res_node[7] REG8B:u5|DOUT[7] } { 0.000ns 0.000ns 2.900ns 0.000ns 0.000ns 0.000ns 2.200ns } { 0.000ns 3.500ns 1.200ns 0.300ns 0.300ns 1.300ns 1.200ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.500 ns + " "Info: + Micro setup delay of destination is 2.500 ns" {  } { { "REG8B.vhd" "" { Text "D:/source/Quartus/backup/DDS_2/REG8B.vhd" 13 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 5.300 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns CLK 1 CLK PIN_55 152 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_55; Fanout = 152; CLK Node = 'CLK'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "DDS_VHDL.vhd" "" { Text "D:/source/Quartus/backup/DDS_2/DDS_VHDL.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns REG8B:u5\|DOUT\[7\] 2 REG LC1_B2 8 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC1_B2; Fanout = 8; REG Node = 'REG8B:u5\|DOUT\[7\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.500 ns" { CLK REG8B:u5|DOUT[7] } "NODE_NAME" } } { "REG8B.vhd" "" { Text "D:/source/Quartus/backup/DDS_2/REG8B.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns ( 52.83 % ) " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns ( 47.17 % ) " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.300 ns" { CLK REG8B:u5|DOUT[7] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.300 ns" { CLK CLK~out REG8B:u5|DOUT[7] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.900 ns" { PWORD[4] ADDER8B:u4|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[4] ADDER8B:u4|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[5] ADDER8B:u4|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[6] ADDER8B:u4|lpm_add_sub:Add0|addcore:adder|unreg_res_node[7] REG8B:u5|DOUT[7] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "12.900 ns" { PWORD[4] PWORD[4]~out ADDER8B:u4|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[4] ADDER8B:u4|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[5] ADDER8B:u4|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[6] ADDER8B:u4|lpm_add_sub:Add0|addcore:adder|unreg_res_node[7] REG8B:u5|DOUT[7] } { 0.000ns 0.000ns 2.900ns 0.000ns 0.000ns 0.000ns 2.200ns } { 0.000ns 3.500ns 1.200ns 0.300ns 0.300ns 1.300ns 1.200ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.300 ns" { CLK REG8B:u5|DOUT[7] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.300 ns" { CLK CLK~out REG8B:u5|DOUT[7] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK FOUT\[6\] SIN_ROM:u3\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[6\]~reg_ra0 31.100 ns memory " "Info: tco from clock \"CLK\" to destination pin \"FOUT\[6\]\" through memory \"SIN_ROM:u3\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[6\]~reg_ra0\" is 31.100 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 5.300 ns + Longest memory " "Info: + Longest clock path from clock \"CLK\" to source memory is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns CLK 1 CLK PIN_55 152 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_55; Fanout = 152; CLK Node = 'CLK'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "DDS_VHDL.vhd" "" { Text "D:/source/Quartus/backup/DDS_2/DDS_VHDL.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns SIN_ROM:u3\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[6\]~reg_ra0 2 MEM EC4_C 1 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = EC4_C; Fanout = 1; MEM Node = 'SIN_ROM:u3\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[6\]~reg_ra0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.500 ns" { CLK SIN_ROM:u3|lpm_rom:lpm_rom_component|altrom:srom|q[6]~reg_ra0 } "NODE_NAME" } } { "altrom.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/altrom.tdf" 80 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns ( 52.83 % ) " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns ( 47.17 % ) " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.300 ns" { CLK SIN_ROM:u3|lpm_rom:lpm_rom_component|altrom:srom|q[6]~reg_ra0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.300 ns" { CLK CLK~out SIN_ROM:u3|lpm_rom:lpm_rom_component|altrom:srom|q[6]~reg_ra0 } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.600 ns + " "Info: + Micro clock to output delay of source is 0.600 ns" {  } { { "altrom.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/altrom.tdf" 80 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "25.200 ns + Longest memory pin " "Info: + Longest memory to pin delay is 25.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns SIN_ROM:u3\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[6\]~reg_ra0 1 MEM EC4_C 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = EC4_C; Fanout = 1; MEM Node = 'SIN_ROM:u3\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[6\]~reg_ra0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { SIN_ROM:u3|lpm_rom:lpm_rom_component|altrom:srom|q[6]~reg_ra0 } "NODE_NAME" } } { "altrom.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/altrom.tdf" 80 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(10.700 ns) 10.700 ns SIN_ROM:u3\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[6\]~mem_cell_ra0 2 MEM EC4_C 1 " "Info: 2: + IC(0.000 ns) + CELL(10.700 ns) = 10.700 ns; Loc. = EC4_C; Fanout = 1; MEM Node = 'SIN_ROM:u3\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[6\]~mem_cell_ra0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.700 ns" { SIN_ROM:u3|lpm_rom:lpm_rom_component|altrom:srom|q[6]~reg_ra0 SIN_ROM:u3|lpm_rom:lpm_rom_component|altrom:srom|q[6]~mem_cell_ra0 } "NODE_NAME" } } { "altrom.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/altrom.tdf" 80 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 13.200 ns SIN_ROM:u3\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[6\] 3 MEM EC4_C 1 " "Info: 3: + IC(0.000 ns) + CELL(2.500 ns) = 13.200 ns; Loc. = EC4_C; Fanout = 1; MEM Node = 'SIN_ROM:u3\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[6\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.500 ns" { SIN_ROM:u3|lpm_rom:lpm_rom_component|altrom:srom|q[6]~mem_cell_ra0 SIN_ROM:u3|lpm_rom:lpm_rom_component|altrom:srom|q[6] } "NODE_NAME" } } { "altrom.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/altrom.tdf" 80 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.700 ns) + CELL(1.800 ns) 17.700 ns FOUT\[6\]~6 4 COMB LC8_C2 1 " "Info: 4: + IC(2.700 ns) + CELL(1.800 ns) = 17.700 ns; Loc. = LC8_C2; Fanout = 1; COMB Node = 'FOUT\[6\]~6'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.500 ns" { SIN_ROM:u3|lpm_rom:lpm_rom_component|altrom:srom|q[6] FOUT[6]~6 } "NODE_NAME" } } { "DDS_VHDL.vhd" "" { Text "D:/source/Quartus/backup/DDS_2/DDS_VHDL.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.400 ns) + CELL(5.100 ns) 25.200 ns FOUT\[6\] 5 PIN PIN_79 0 " "Info: 5: + IC(2.400 ns) + CELL(5.100 ns) = 25.200 ns; Loc. = PIN_79; Fanout = 0; PIN Node = 'FOUT\[6\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.500 ns" { FOUT[6]~6 FOUT[6] } "NODE_NAME" } } { "DDS_VHDL.vhd" "" { Text "D:/source/Quartus/backup/DDS_2/DDS_VHDL.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "20.100 ns ( 79.76 % ) " "Info: Total cell delay = 20.100 ns ( 79.76 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.100 ns ( 20.24 % ) " "Info: Total interconnect delay = 5.100 ns ( 20.24 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "25.200 ns" { SIN_ROM:u3|lpm_rom:lpm_rom_component|altrom:srom|q[6]~reg_ra0 SIN_ROM:u3|lpm_rom:lpm_rom_component|altrom:srom|q[6]~mem_cell_ra0 SIN_ROM:u3|lpm_rom:lpm_rom_component|al