dds_vhdl.tan.qmsg

来自「rom地址宽度8位」· QMSG 代码 · 共 10 行 · 第 1/5 页

QMSG
10 行
字号
12345
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register REG30B:u2\|DOUT\[16\] register REG30B:u2\|DOUT\[31\] 59.88 MHz 16.7 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 59.88 MHz between source register \"REG30B:u2\|DOUT\[16\]\" and destination register \"REG30B:u2\|DOUT\[31\]\" (period= 16.7 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "13.100 ns + Longest register register " "Info: + Longest register to register delay is 13.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns REG30B:u2\|DOUT\[16\] 1 REG LC1_B14 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_B14; Fanout = 2; REG Node = 'REG30B:u2\|DOUT\[16\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { REG30B:u2|DOUT[16] } "NODE_NAME" } } { "REG30B.VHDL" "" { Text "D:/source/Quartus/backup/DDS_2/REG30B.VHDL" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(1.200 ns) 3.400 ns ADDER30B:u1\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[0\] 2 COMB LC1_B13 2 " "Info: 2: + IC(2.200 ns) + CELL(1.200 ns) = 3.400 ns; Loc. = LC1_B13; Fanout = 2; COMB Node = 'ADDER30B:u1\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.400 ns" { REG30B:u2|DOUT[16] ADDER30B:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[0] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 3.700 ns ADDER30B:u1\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[1\] 3 COMB LC2_B13 2 " "Info: 3: + IC(0.000 ns) + CELL(0.300 ns) = 3.700 ns; Loc. = LC2_B13; Fanout = 2; COMB Node = 'ADDER30B:u1\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.300 ns" { ADDER30B:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[0] ADDER30B:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[1] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 4.000 ns ADDER30B:u1\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[2\] 4 COMB LC3_B13 2 " "Info: 4: + IC(0.000 ns) + CELL(0.300 ns) = 4.000 ns; Loc. = LC3_B13; Fanout = 2; COMB Node = 'ADDER30B:u1\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[2\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.300 ns" { ADDER30B:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[1] ADDER30B:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[2] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 4.300 ns ADDER30B:u1\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[3\] 5 COMB LC4_B13 2 " "Info: 5: + IC(0.000 ns) + CELL(0.300 ns) = 4.300 ns; Loc. = LC4_B13; Fanout = 2; COMB Node = 'ADDER30B:u1\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.300 ns" { ADDER30B:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[2] ADDER30B:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[3] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 4.600 ns ADDER30B:u1\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[4\] 6 COMB LC5_B13 2 " "Info: 6: + IC(0.000 ns) + CELL(0.300 ns) = 4.600 ns; Loc. = LC5_B13; Fanout = 2; COMB Node = 'ADDER30B:u1\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[4\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.300 ns" { ADDER30B:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[3] ADDER30B:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[4] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 4.900 ns ADDER30B:u1\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[5\] 7 COMB LC6_B13 2 " "Info: 7: + IC(0.000 ns) + CELL(0.300 ns) = 4.900 ns; Loc. = LC6_B13; Fanout = 2; COMB Node = 'ADDER30B:u1\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[5\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.300 ns" { ADDER30B:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[4] ADDER30B:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[5] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 5.200 ns ADDER30B:u1\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[6\] 8 COMB LC7_B13 2 " "Info: 8: + IC(0.000 ns) + CELL(0.300 ns) = 5.200 ns; Loc. = LC7_B13; Fanout = 2; COMB Node = 'ADDER30B:u1\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[6\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.300 ns" { ADDER30B:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[5] ADDER30B:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[6] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 5.500 ns ADDER30B:u1\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[7\] 9 COMB LC8_B13 2 " "Info: 9: + IC(0.000 ns) + CELL(0.300 ns) = 5.500 ns; Loc. = LC8_B13; Fanout = 2; COMB Node = 'ADDER30B:u1\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[7\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.300 ns" { ADDER30B:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[6] ADDER30B:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[7] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.800 ns) + CELL(0.300 ns) 6.600 ns ADDER30B:u1\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[8\] 10 COMB LC1_B15 2 " "Info: 10: + IC(0.800 ns) + CELL(0.300 ns) = 6.600 ns; Loc. = LC1_B15; Fanout = 2; COMB Node = 'ADDER30B:u1\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[8\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.100 ns" { ADDER30B:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[7] ADDER30B:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[8] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 6.900 ns ADDER30B:u1\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[9\] 11 COMB LC2_B15 2 " "Info: 11: + IC(0.000 ns) + CELL(0.300 ns) = 6.900 ns; Loc. = LC2_B15; Fanout = 2; COMB Node = 'ADDER30B:u1\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[9\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.300 ns" { ADDER30B:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[8] ADDER30B:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[9] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 7.200 ns ADDER30B:u1\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[10\] 12 COMB LC3_B15 2 " "Info: 12: + IC(0.000 ns) + CELL(0.300 ns) = 7.200 ns; Loc. = LC3_B15; Fanout = 2; COMB Node = 'ADDER30B:u1\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[10\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.300 ns" { ADDER30B:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[9] ADDER30B:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[10] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 7.500 ns ADDER30B:u1\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[11\] 13 COMB LC4_B15 2 " "Info: 13: + IC(0.000 ns) + CELL(0.300 ns) = 7.500 ns; Loc. = LC4_B15; Fanout = 2; COMB Node = 'ADDER30B:u1\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[11\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.300 ns" { ADDER30B:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[10] ADDER30B:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[11] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 7.800 ns ADDER30B:u1\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[12\] 14 COMB LC5_B15 2 " "Info: 14: + IC(0.000 ns) + CELL(0.300 ns) = 7.800 ns; Loc. = LC5_B15; Fanout = 2; COMB Node = 'ADDER30B:u1\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[12\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.300 ns" { ADDER30B:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[11] ADDER30B:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[12] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 8.100 ns ADDER30B:u1\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[13\] 15 COMB LC6_B15 2 " "Info: 15: + IC(0.000 ns) + CELL(0.300 ns) = 8.100 ns; Loc. = LC6_B15; Fanout = 2; COMB Node = 'ADDER30B:u1\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[13\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.300 ns" { ADDER30B:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[12] ADDER30B:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[13] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 8.400 ns ADDER30B:u1\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[14\] 16 COMB LC7_B15 1 " "Info: 16: + IC(0.000 ns) + CELL(0.300 ns) = 8.400 ns; Loc. = LC7_B15; Fanout = 1; COMB Node = 'ADDER30B:u1\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[14\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.300 ns" { ADDER30B:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[13] ADDER30B:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[14] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 9.700 ns ADDER30B:u1\|lpm_add_sub:Add0\|addcore:adder\|unreg_res_node\[15\] 17 COMB LC8_B15 1 " "Info: 17: + IC(0.000 ns) + CELL(1.300 ns) = 9.700 ns; Loc. = LC8_B15; Fanout = 1; COMB Node = 'ADDER30B:u1\|lpm_add_sub:Add0\|addcore:adder\|unreg_res_node\[15\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.300 ns" { ADDER30B:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[14] ADDER30B:u1|lpm_add_sub:Add0|addcore:adder|unreg_res_node[15] } "NODE_NAME" } } { "addcore.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/addcore.tdf" 95 16 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(1.200 ns) 13.100 ns REG30B:u2\|DOUT\[31\] 18 REG LC6_B16 10 " "Info: 18: + IC(2.200 ns) + CELL(1.200 ns) = 13.100 ns; Loc. = LC6_B16; Fanout = 10; REG Node = 'REG30B:u2\|DOUT\[31\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.400 ns" { ADDER30B:u1|lpm_add_sub:Add0|addcore:adder|unreg_res_node[15] REG30B:u2|DOUT[31] } "NODE_NAME" } } { "REG30B.VHDL" "" { Text "D:/source/Quartus/backup/DDS_2/REG30B.VHDL" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.900 ns ( 60.31 % ) " "Info: Total cell delay = 7.900 ns ( 60.31 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.200 ns ( 39.69 % ) " "Info: Total interconnect delay = 5.200 ns ( 39.69 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "13.100 ns" { REG30B:u2|DOUT[16] ADDER30B:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[0] ADDER30B:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[1] ADDER30B:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[2] ADDER30B:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[3] ADDER30B:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[4] ADDER30B:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[5] ADDER30B:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[6] ADDER30B:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[7] ADDER30B:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[8] ADDER30B:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[9] ADDER30B:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[10] ADDER30B:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[11] ADDER30B:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[12] ADDER30B:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[13] ADDER30B:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[14] ADDER30B:u1|lpm_add_sub:Add0|addcore:adder|unreg_res_node[15] REG30B:u2|DOUT[31] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "13.100 ns" { REG30B:u2|DOUT[16] ADDER30B:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[0] ADDER30B:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[1] ADDER30B:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[2] ADDER30B:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[3] ADDER30B:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[4] ADDER30B:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[5] ADDER30B:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[6] ADDER30B:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[7] ADDER30B:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[8] ADDER30B:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[9] ADDER30B:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[10] ADDER30B:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[11] ADDER30B:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[12] ADDER30B:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[13] ADDER30B:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[14] ADDER30B:u1|lpm_add_sub:Add0|addcore:adder|unreg_res_node[15] REG30B:u2|DOUT[31] } { 0.000ns 2.200ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.800ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 2.200ns } { 0.000ns 1.200ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 1.300ns 1.200ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 5.300 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns CLK 1 CLK PIN_55 152 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_55; Fanout = 152; CLK Node = 'CLK'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "DDS_VHDL.vhd" "" { Text "D:/source/Quartus/backup/DDS_2/DDS_VHDL.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns REG30B:u2\|DOUT\[31\] 2 REG LC6_B16 10 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC6_B16; Fanout = 10; REG Node = 'REG30B:u2\|DOUT\[31\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.500 ns" { CLK REG30B:u2|DOUT[31] } "NODE_NAME" } } { "REG30B.VHDL" "" { Text "D:/source/Quartus/backup/DDS_2/REG30B.VHDL" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns ( 52.83 % ) " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns ( 47.17 % ) " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.300 ns" { CLK REG30B:u2|DOUT[31] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.300 ns" { CLK CLK~out REG30B:u2|DOUT[31] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 5.300 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns CLK 1 CLK PIN_55 152 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_55; Fanout = 152; CLK Node = 'CLK'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "DDS_VHDL.vhd" "" { Text "D:/source/Quartus/backup/DDS_2/DDS_VHDL.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns REG30B:u2\|DOUT\[16\] 2 REG LC1_B14 2 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC1_B14; Fanout = 2; REG Node = 'REG30B:u2\|DOUT\[16\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.500 ns" { CLK REG30B:u2|DOUT[16] } "NODE_NAME" } } { "REG30B.VHDL" "" { Text "D:/source/Quartus/backup/DDS_2/REG30B.VHDL" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns ( 52.83 % ) " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns ( 47.17 % ) " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.300 ns" { CLK REG30B:u2|DOUT[16] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.300 ns" { CLK CLK~out REG30B:u2|DOUT[16] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.300 ns" { CLK REG30B:u2|DOUT[31] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.300 ns" { CLK CLK~out REG30B:u2|DOUT[31] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.300 ns" { CLK REG30B:u2|DOUT[16] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.300 ns" { CLK CLK~out REG30B:u2|DOUT[16] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "REG30B.VHDL" "" { Text "D:/source/Quartus/backup/DDS_2/REG30B.VHDL" 13 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.500 ns + " "Info: + Micro setup delay of destination is 2.500 ns" {  } { { "REG30B.VHDL" "" { Text "D:/source/Quartus/backup/DDS_2/REG30B.VHDL" 13 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "13.100 ns" { REG30B:u2|DOUT[16] ADDER30B:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[0] ADDER30B:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[1] ADDER30B:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[2] ADDER30B:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[3] ADDER30B:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[4] ADDER30B:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[5] ADDER30B:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[6] ADDER30B:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[7] ADDER30B:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[8] ADDER30B:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[9] ADDER30B:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[10] ADDER30B:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[11] ADDER30B:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[12] ADDER30B:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[13] ADDER30B:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[14] ADDER30B:u1|lpm_add_sub:Add0|addcore:adder|unreg_res_node[15] REG30B:u2|DOUT[31] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "13.100 ns" { REG30B:u2|DOUT[16] ADDER30B:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[0] ADDER30B:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[1] ADDER30B:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[2] ADDER30B:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[3] ADDER30B:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[4] ADDER30B:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[5] ADDER30B:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[6] ADDER30B:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[7] ADDER30B:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[8] ADDER30B:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[9] ADDER30B:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[10] ADDER30B:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[11] ADDER30B:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[12] ADDER30B:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[13] ADDER30B:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[14] ADDER30B:u1|lpm_add_sub:Add0|addcore:adder|unreg_res_node[15] REG30B:u2|DOUT[31] } { 0.000ns 2.200ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.800ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 2.200ns } { 0.000ns 1.200ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 1.300ns 1.200ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.300 ns" { CLK REG30B:u2|DOUT[31] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.300 ns" { CLK CLK~out REG30B:u2|DOUT[31] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.300 ns" { CLK REG30B:u2|DOUT[16] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.300 ns" { CLK CLK~out REG30B:u2|DOUT[16] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "key register F30B\[16\] register F30B\[23\] 74.63 MHz 13.4 ns Internal " "Info: Clock \"key\" has Internal fmax of 74.63 MHz between source register \"F30B\[16\]\" and destination register \"F30B\[23\]\" (period= 13.4 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.900 ns + Longest register register " "Info: + Longest register to register delay is 9.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns F30B\[16\] 1 REG LC1_A15 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_A15; Fanout = 4; REG Node = 'F30B\[16\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { F30B[16] } "NODE_NAME" } } { "DDS_VHDL.vhd" "" { Text "D:/source/Quartus/backup/DDS_2/DDS_VHDL.vhd" 57 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(1.200 ns) 3.400 ns lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[0\] 2 COMB LC1_A17 2 " "Info: 2: + IC(2.200 ns) + CELL(1.200 ns) = 3.400 ns; Loc. = LC1_A17; Fanout = 2; COMB Node = 'lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.400 ns" { F30B[16] lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[0] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 3.700 ns lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[1\] 3 COMB LC2_A17 2 " "Info: 3: + IC(0.000 ns) + CELL(0.300 ns) = 3.700 ns; Loc. = LC2_A17; Fanout = 2; COMB Node = 'lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.300 ns" { lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[0] lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[1] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 4.000 ns lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[2\] 4 COMB LC3_A17 2 " "Info: 4: + IC(0.000 ns) + CELL(0.300 ns) = 4.000 ns; Loc. = LC3_A17; Fanout = 2; COMB Node = 'lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[2\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.300 ns" { lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[1] lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[2] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 4.300 ns lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[3\] 5 COMB LC4_A17 2 " "Info: 5: + IC(0.000 ns) + CELL(0.300 ns) = 4.300 ns; Loc. = LC4_A17; Fanout = 2; COMB Node = 'lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.300 ns" { lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[2] lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[3] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 4.600 ns lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[4\] 6 COMB LC5_A17 2 " "Info: 6: + IC(0.000 ns) + CELL(0.300 ns) = 4.600 ns; Loc. = LC5_A17; Fanout = 2; COMB Node = 'lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[4\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.300 ns" { lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[3] lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[4] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 4.900 ns lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[5\] 7 COMB LC6_A17 2 " "Info: 7: + IC(0.000 ns) + CELL(0.300 ns) = 4.900 ns; Loc. = LC6_A17; Fanout = 2; COMB Node = 'lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[5\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.300 ns" { lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[4] lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[5] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 5.200 ns lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[6\] 8 COMB LC7_A17 1 " "Info: 8: + IC(0.000 ns) + CELL(0.300 ns) = 5.200 ns; Loc. = LC7_A17; Fanout = 1; COMB Node = 'lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[6\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.300 ns" { lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[5] lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[6] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 6.500 ns lpm_add_sub:Add0\|addcore:adder\|unreg_res_node\[7\] 9 COMB LC8_A17 1 " "Info: 9: + IC(0.000 ns) + CELL(1.300 ns) = 6.500 ns; Loc. = LC8_A17; Fanout = 1; COMB Node = 'lpm_add_sub:Add0\|addcore:adder\|unreg_res_node\[7\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.300 ns" { lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[6] lpm_add_sub:Add0|addcore:adder|unreg_res_node[7] } "NODE_NAME" } } { "addcore.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/addcore.tdf" 95 16 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(1.200 ns) 9.900 ns F30B\[23\] 10 REG LC8_A13 3 " "Info: 10: + IC(2.200 ns) + CELL(1.200 ns) = 9.900 ns; Loc. = LC8_A13; Fanout = 3; REG Node = 'F30B\[23\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.400 ns" { lpm_add_sub:Add0|addcore:adder|unreg_res_node[7] F30B[23] } "NODE_NAME" } } { "DDS_VHDL.vhd" "" { Text "D:/source/Quartus/backup/DDS_2/DDS_VHDL.vhd" 57 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.500 ns ( 55.56 % ) " "Info: Total cell delay = 5.500 ns ( 55.56 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.400 ns ( 44.44 % ) " "Info: Total interconnect delay = 4.400 ns ( 44.44 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.900 ns" { F30B[16] lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[0] lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[1] lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[2] lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[3] lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[4] lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[5] lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[6] lpm_add_sub:Add0|addcore:adder|unreg_res_node[7] F30B[23] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "9.900 ns" { F30B[16] lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[0] lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[1] lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[2] lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[3] lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[4] lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[5] lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[6] lpm_add_sub:Add0|addcore:adder|unreg_res_node[7] F30B[23] } { 0.000ns 2.200ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 2.200ns } { 0.000ns 1.200ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 1.300ns 1.200ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.100 ns - Smallest " "Info: - Smallest clock skew is 0.100 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "key destination 9.700 ns + Shortest register " "Info: + Shortest clock path from clock \"key\" to destination register is 9.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.500 ns) 3.500 ns key 1 CLK PIN_20 8 " "Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_20; Fanout = 8; CLK Node = 'key'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { key } "NODE_NAME" } } { "DDS_VHDL.vhd" "" { Text "D:/source/Quartus/backup/DDS_2/DDS_VHDL.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.200 ns) + CELL(0.000 ns) 9.700 ns F30B\[23\] 2 REG LC8_A13 3 " "Info: 2: + IC(6.200 ns) + CELL(0.000 ns) = 9.700 ns; Loc. = LC8_A13; Fanout = 3; REG Node = 'F30B\[23\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.200 ns" { key F30B[23] } "NODE_NAME" } } { "DDS_VHDL.vhd" "" { Text "D:/source/Quartus/backup/DDS_2/DDS_VHDL.vhd" 57 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.500 ns ( 36.08 % ) " "Info: Total cell delay = 3.500 ns ( 36.08 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.200 ns ( 63.92 % ) " "Info: Total interconnect delay = 6.200 ns ( 63.92 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.700 ns" { key F30B[23] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "9.700 ns" { key key~out F30B[23] } { 0.000ns 0.000ns 6.200ns } { 0.000ns 3.500ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "key source 9.600 ns - Longest register " "Info: - Longest clock path from clock \"key\" to source register is 9.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.500 ns) 3.500 ns key 1 CLK PIN_20 8 " "Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_20; Fanout = 8; CLK Node = 'key'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { key } "NODE_NAME" } } { "DDS_VHDL.vhd" "" { Text "D:/source/Quartus/backup/DDS_2/DDS_VHDL.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.100 ns) + CELL(0.000 ns) 9.600 ns F30B\[16\] 2 REG LC1_A15 4 " "Info: 2: + IC(6.100 ns) + CELL(0.000 ns) = 9.600 ns; Loc. = LC1_A15; Fanout = 4; REG Node = 'F30B\[16\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.100 ns" { key F30B[16] } "NODE_NAME" } } { "DDS_VHDL.vhd" "" { Text "D:/source/Quartus/backup/DDS_2/DDS_VHDL.vhd" 57 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.500 ns ( 36.46 % ) " "Info: Total cell delay = 3.500 ns ( 36.46 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.100 ns ( 63.54 % ) " "Info: Total interconnect delay = 6.100 ns ( 63.54 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.600 ns" { key F30B[16] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "9.600 ns" { key key~out F30B[16] } { 0.000ns 0.000ns 6.100ns } { 0.000ns 3.500ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.700 ns" { key F30B[23] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "9.700 ns" { key key~out F30B[23] } { 0.000ns 0.000ns 6.200ns } { 0.000ns 3.500ns 0.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.600 ns" { key F30B[16] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "9.600 ns" { key key~out F30B[16] } { 0.000ns 0.000ns 6.100ns } { 0.000ns 3.500ns 0.000ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "DDS_VHDL.vhd" "" { Text "D:/source/Quartus/backup/DDS_2/DDS_VHDL.vhd" 57 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.500 ns + " "Info: + Micro setup delay of destination is 2.500 ns" {  } { { "DDS_VHDL.vhd" "" { Text "D:/source/Quartus/backup/DDS_2/DDS_VHDL.vhd" 57 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.900 ns" { F30B[16] lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[0] lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[1] lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[2] lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[3] lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[4] lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[5] lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[6] lpm_add_sub:Add0|addcore:adder|unreg_res_node[7] F30B[23] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "9.900 ns" { F30B[16] lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[0] lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[1] lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[2] lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[3] lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[4] lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[5] lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[6] lpm_add_sub:Add0|addcore:adder|unreg_res_node[7] F30B[23] } { 0.000ns 2.200ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 2.200ns } { 0.000ns 1.200ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 1.300ns 1.200ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.700 ns" { key F30B[23] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "9.700 ns" { key key~out F30B[23] } { 0.000ns 0.000ns 6.200ns } { 0.000ns 3.500ns 0.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.600 ns" { key F30B[16] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "9.600 ns" { key key~out F30B[16] } { 0.000ns 0.000ns 6.100ns } { 0.000ns 3.500ns 0.000ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
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dds_vhdl.tan.qmsg - 源码说明

本页面展示了「rom地址宽度8位」中的 dds_vhdl.tan.qmsg 源码文件，采用 QMSG 编程语言编写，共 10 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。

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