dds_vhdl.map.qmsg

来自「rom地址宽度8位」· QMSG 代码 · 共 91 行 · 第 1/4 页

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Dec 28 17:35:12 2007 " "Info: Processing started: Fri Dec 28 17:35:12 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off DDS_VHDL -c DDS_VHDL " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off DDS_VHDL -c DDS_VHDL" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ADDER30B.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ADDER30B.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ADDER30B-behav " "Info: Found design unit 1: ADDER30B-behav" {  } { { "ADDER30B.vhd" "" { Text "D:/source/Quartus/backup/DDS_2/ADDER30B.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 ADDER30B " "Info: Found entity 1: ADDER30B" {  } { { "ADDER30B.vhd" "" { Text "D:/source/Quartus/backup/DDS_2/ADDER30B.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ADDER8B.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ADDER8B.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ADDER8B-behav " "Info: Found design unit 1: ADDER8B-behav" {  } { { "ADDER8B.vhd" "" { Text "D:/source/Quartus/backup/DDS_2/ADDER8B.vhd" 9 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 ADDER8B " "Info: Found entity 1: ADDER8B" {  } { { "ADDER8B.vhd" "" { Text "D:/source/Quartus/backup/DDS_2/ADDER8B.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "DDS_VHDL.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file DDS_VHDL.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 DDS_VHDL-one " "Info: Found design unit 1: DDS_VHDL-one" {  } { { "DDS_VHDL.vhd" "" { Text "D:/source/Quartus/backup/DDS_2/DDS_VHDL.vhd" 17 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 DDS_VHDL " "Info: Found entity 1: DDS_VHDL" {  } { { "DDS_VHDL.vhd" "" { Text "D:/source/Quartus/backup/DDS_2/DDS_VHDL.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "REG30B.VHDL 2 1 " "Info: Found 2 design units, including 1 entities, in source file REG30B.VHDL" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 REG30B-behav " "Info: Found design unit 1: REG30B-behav" {  } { { "REG30B.VHDL" "" { Text "D:/source/Quartus/backup/DDS_2/REG30B.VHDL" 9 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 REG30B " "Info: Found entity 1: REG30B" {  } { { "REG30B.VHDL" "" { Text "D:/source/Quartus/backup/DDS_2/REG30B.VHDL" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "REG8B.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file REG8B.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 REG8B-behav " "Info: Found design unit 1: REG8B-behav" {  } { { "REG8B.vhd" "" { Text "D:/source/Quartus/backup/DDS_2/REG8B.vhd" 9 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 REG8B " "Info: Found entity 1: REG8B" {  } { { "REG8B.vhd" "" { Text "D:/source/Quartus/backup/DDS_2/REG8B.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "DDS_VHDL " "Info: Elaborating entity \"DDS_VHDL\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_NET" "F30B\[31\] X DDS_VHDL.vhd(45) " "Warning (10030): Tied undriven net \"F30B\[31\]\" at DDS_VHDL.vhd(45) to X" {  } { { "DDS_VHDL.vhd" "" { Text "D:/source/Quartus/backup/DDS_2/DDS_VHDL.vhd" 45 0 0 } }  } 0 10030 "Tied undriven net \"%1!s!\" at %3!s! to %2!s!" 0 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_NET" "F30B\[30\] X DDS_VHDL.vhd(45) " "Warning (10030): Tied undriven net \"F30B\[30\]\" at DDS_VHDL.vhd(45) to X" {  } { { "DDS_VHDL.vhd" "" { Text "D:/source/Quartus/backup/DDS_2/DDS_VHDL.vhd" 45 0 0 } }  } 0 10030 "Tied undriven net \"%1!s!\" at %3!s! to %2!s!" 0 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_NET" "F30B\[29\] X DDS_VHDL.vhd(45) " "Warning (10030): Tied undriven net \"F30B\[29\]\" at DDS_VHDL.vhd(45) to X" {  } { { "DDS_VHDL.vhd" "" { Text "D:/source/Quartus/backup/DDS_2/DDS_VHDL.vhd" 45 0 0 } }  } 0 10030 "Tied undriven net \"%1!s!\" at %3!s! to %2!s!" 0 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_NET" "F30B\[28\] X DDS_VHDL.vhd(45) " "Warning (10030): Tied undriven net \"F30B\[28\]\" at DDS_VHDL.vhd(45) to X" {  } { { "DDS_VHDL.vhd" "" { Text "D:/source/Quartus/backup/DDS_2/DDS_VHDL.vhd" 45 0 0 } }  } 0 10030 "Tied undriven net \"%1!s!\" at %3!s! to %2!s!" 0 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_NET" "F30B\[27\] X DDS_VHDL.vhd(45) " "Warning (10030): Tied undriven net \"F30B\[27\]\" at DDS_VHDL.vhd(45) to X" {  } { { "DDS_VHDL.vhd" "" { Text "D:/source/Quartus/backup/DDS_2/DDS_VHDL.vhd" 45 0 0 } }  } 0 10030 "Tied undriven net \"%1!s!\" at %3!s! to %2!s!" 0 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_NET" "F30B\[26\] X DDS_VHDL.vhd(45) " "Warning (10030): Tied undriven net \"F30B\[26\]\" at DDS_VHDL.vhd(45) to X" {  } { { "DDS_VHDL.vhd" "" { Text "D:/source/Quartus/backup/DDS_2/DDS_VHDL.vhd" 45 0 0 } }  } 0 10030 "Tied undriven net \"%1!s!\" at %3!s! to %2!s!" 0 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_NET" "F30B\[25\] X DDS_VHDL.vhd(45) " "Warning (10030): Tied undriven net \"F30B\[25\]\" at DDS_VHDL.vhd(45) to X" {  } { { "DDS_VHDL.vhd" "" { Text "D:/source/Quartus/backup/DDS_2/DDS_VHDL.vhd" 45 0 0 } }  } 0 10030 "Tied undriven net \"%1!s!\" at %3!s! to %2!s!" 0 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_NET" "F30B\[24\] X DDS_VHDL.vhd(45) " "Warning (10030): Tied undriven net \"F30B\[24\]\" at DDS_VHDL.vhd(45) to X" {  } { { "DDS_VHDL.vhd" "" { Text "D:/source/Quartus/backup/DDS_2/DDS_VHDL.vhd" 45 0 0 } }  } 0 10030 "Tied undriven net \"%1!s!\" at %3!s! to %2!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ADDER30B ADDER30B:u1 " "Info: Elaborating entity \"ADDER30B\" for hierarchy \"ADDER30B:u1\"" {  } { { "DDS_VHDL.vhd" "u1" { Text "D:/source/Quartus/backup/DDS_2/DDS_VHDL.vhd" 70 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "REG30B REG30B:u2 " "Info: Elaborating entity \"REG30B\" for hierarchy \"REG30B:u2\"" {  } { { "DDS_VHDL.vhd" "u2" { Text "D:/source/Quartus/backup/DDS_2/DDS_VHDL.vhd" 71 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "SIN_ROM.vhd 2 1 " "Warning: Using design file SIN_ROM.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sin_rom-SYN " "Info: Found design unit 1: sin_rom-SYN" {  } { { "SIN_ROM.vhd" "" { Text "D:/source/Quartus/backup/DDS_2/SIN_ROM.vhd" 49 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 SIN_ROM " "Info: Found entity 1: SIN_ROM" {  } { { "SIN_ROM.vhd" "" { Text "D:/source/Quartus/backup/DDS_2/SIN_ROM.vhd" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "SIN_ROM SIN_ROM:u3 " "Info: Elaborating entity \"SIN_ROM\" for hierarchy \"SIN_ROM:u3\"" {  } { { "DDS_VHDL.vhd" "u3" { Text "D:/source/Quartus/backup/DDS_2/DDS_VHDL.vhd" 72 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus60/libraries/megafunctions/lpm_rom.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus60/libraries/megafunctions/lpm_rom.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_rom " "Info: Found entity 1: lpm_rom" {  } { { "lpm_rom.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/lpm_rom.tdf" 41 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_rom SIN_ROM:u3\|lpm_rom:lpm_rom_component " "Info: Elaborating entity \"lpm_rom\" for hierarchy \"SIN_ROM:u3\|lpm_rom:lpm_rom_component\"" {  } { { "SIN_ROM.vhd" "lpm_rom_component" { Text "D:/source/Quartus/backup/DDS_2/SIN_ROM.vhd" 75 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}