adder8b.vhd

来自「rom地址宽度8位」· VHDL 代码 · 共 12 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY ADDER8B IS
    PORT (  A : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
            B : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
            S : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)     );
END ADDER8B;
ARCHITECTURE behav OF ADDER8B IS
    BEGIN
	S <= A + B;
END behav;