dds_vhdl.vhd

rom地址宽度8位

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY DDS_VHDL IS                                     -- 顶层设计
    PORT (  
          FOUT  : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);   --可移相正弦信号输出
          POUT  : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); --参考信号输出		  
		  CLK   : IN  STD_LOGIC;  --系统时钟
          PWORD : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);  --相位控制字
 			key: in std_logic;
			clear:in std_logic;
			mode :in std_logic
          );
 END;

ARCHITECTURE one OF DDS_VHDL IS

COMPONENT REG30B                    --30位锁存器
        PORT (  LOAD : IN STD_LOGIC;
                 DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
                DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) );
    	END COMPONENT;
COMPONENT REG8B                   --8位锁存器
        PORT (  LOAD :  IN STD_LOGIC;
                 DIN :  IN STD_LOGIC_VECTOR(7 DOWNTO 0);
                DOUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) );
   		END COMPONENT;
COMPONENT ADDER30B                  --30位加法器
       PORT (  A : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
               B : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
               S : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)     );
   	   END COMPONENT;
COMPONENT ADDER8B                   --8位加法器
       PORT (  A : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
                B : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
                S : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)     );
   	   END COMPONENT;
COMPONENT SIN_ROM      --8位地址8位数据正弦信号数据ROM
       PORT	( address	: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
		      inclock	: IN STD_LOGIC ;
       	q	: OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
       END COMPONENT; 

 SIGNAL F30B   : STD_LOGIC_VECTOR(31 DOWNTO 0);
     SIGNAL D30B   : STD_LOGIC_VECTOR(31 DOWNTO 0);
     SIGNAL DIN30B : STD_LOGIC_VECTOR(31 DOWNTO 0);
     SIGNAL P8B    : STD_LOGIC_VECTOR( 7 DOWNTO 0);
     SIGNAL LIN8B  : STD_LOGIC_VECTOR( 7 DOWNTO 0);
     SIGNAL SIN8B  : STD_LOGIC_VECTOR( 7 DOWNTO 0);
     SIGNAL q	   :  STD_LOGIC_VECTOR(7 DOWNTO 0);

 BEGIN 

process(key,clear)
 begin
 if(clear='1')   then
    F30B(23 DOWNTO 16)<="00000001";
	elsif key'event and key='1'  then
	  F30B(23 DOWNTO 16)<=F30B(23 DOWNTO 16)+q;
	end if;
 end process;
	
 q <="00000001" when mode='0' else
	 "00001000" ;
	
 F30B(15 DOWNTO 0)<="0000000000000000" ;
 P8B( 7 DOWNTO 0)<=PWORD ; 
 
 u1:ADDER30B  PORT MAP( A=>F30B,B=>D30B, S=>DIN30B );
 u2:REG30B PORT MAP( DOUT=>D30B,DIN=> DIN30B, LOAD=>CLK );
 u3:SIN_ROM PORT MAP(address=>SIN8B,q=>FOUT,inclock=>CLK );
 u4:ADDER8B PORT MAP(A=>P8B,B=>D30B(31 DOWNTO 24),S=>LIN8B );
 u5:REG8B  PORT MAP( DOUT=>SIN8B,DIN=>LIN8B, LOAD=>CLK );
 u6:SIN_ROM  PORT MAP( address=>D30B(31 DOWNTO 24), q=>POUT, 
                     inclock=>CLK );
END;