dds_vhdl.tan.summary

rom地址宽度8位

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 10.100 ns
From           : PWORD[4]
To             : REG8B:u5|DOUT[7]
From Clock     : --
To Clock       : CLK
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 31.100 ns
From           : SIN_ROM:u3|lpm_rom:lpm_rom_component|altrom:srom|q[6]~reg_ra7
To             : FOUT[6]
From Clock     : CLK
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -1.400 ns
From           : mode
To             : F30B[19]
From Clock     : --
To Clock       : key
Failed Paths   : 0

Type           : Clock Setup: 'CLK'
Slack          : N/A
Required Time  : None
Actual Time    : 59.88 MHz ( period = 16.700 ns )
From           : REG30B:u2|DOUT[16]
To             : REG30B:u2|DOUT[31]
From Clock     : CLK
To Clock       : CLK
Failed Paths   : 0

Type           : Clock Setup: 'key'
Slack          : N/A
Required Time  : None
Actual Time    : 74.63 MHz ( period = 13.400 ns )
From           : F30B[16]
To             : F30B[23]
From Clock     : key
To Clock       : key
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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