dds_vhdl.fit.summary

rom地址宽度8位

Fitter Status : Successful - Fri Dec 28 17:35:35 2007
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Full Version
Revision Name : DDS_VHDL
Top-level Entity Name : DDS_VHDL
Family : FLEX10K
Device : EPF10K10TC144-4
Timing Models : Final
Total logic elements : 80 / 576 ( 14 % )
Total pins : 28 / 102 ( 27 % )
Total memory bits : 4,096 / 6,144 ( 67 % )