cnt3.vhd

VHDL的课程设计

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt3 is
	port(clk,en	:in std_logic;
        q  	:buffer std_logic_vector(1 downto 0));
end cnt3;

architecture behav of cnt3 is
begin
process(en,clk)
begin
if (clk'event and clk='1') then
if(en='1')then
if q="11" then q<="00";
ELSE   
q<=q+1;
end if;
end if;
end  if;
end process;
end behav;