icontrol.vhd

VHDL的课程设计

library ieee;
use ieee.std_logic_1164.all;
Entity icontrol is
port(i_set,set,start,iopen,result,clk1,clk:in std_logic;
     en,green,red,jibao:out std_logic);
end icontrol;
Architecture  icontrol_1 of icontrol is
  type states is(st0,st1,st2,st3,st4,st5);
  signal st:states;
  signal sp:std_logic;
begin
  process(i_set,set,start,iopen,result,clk1,clk)
  begin 
    if(i_set='1')then 
     en<='0';green<='0';red<='0';sp<='0';
    elsif(clk'event and clk='1') then
     case st is
       when st0=>en<='0';green<='0';red<='0';sp<='0';
             if(start='1')then
                st<=st1;
             else
                st<=st0;
             end if;
       when st1=>en<='1';green<='0';red<='0';sp<='0';
            if(result='1')then
                st<=st2;
            elsif(iopen='1')then
                st<=st4;
            elsif(set='1')then
                st<=st0;
            else
                st<=st1;
            end if;
       when st2=>en<='1';green<='0';red<='0';sp<='0';
            if(iopen='1')then
                st<=st3;
            elsif(set='1')then
                st<=st0;
            else
                st<=st2;
            end if;
       when st3=>en<='0';green<='1';red<='0';sp<='0';
             if(set='1')then
                st<=st0;
             else
                st<=st3;
             end if;
       when  st4=>en<='1';green<='0';red<='1';sp<='0';
             if(result='1')then
                st<=st2;
            elsif(set='1')then
                st<=st0;
            elsif(result='0' and iopen='1')then
                st<=st5;
            else
                st<=st4;
            end if;
        when  st5=>en<='0';green<='0';red<='1';sp<='1';
           if(set='1')then
                st<=st0;
            else
                st<=st5;
            end if;
       when  others=>st<=st0;
     end case;
  end if;
end process;
 jibao<=(sp and clk1);
end icontrol_1;