📄 mimasuo1.rpt
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_LC4_C5 = LCELL( _EQ011);
_EQ011 = S1 & !S2
# !S0 & !S2;
-- Node name is '|BMQ1:26|:365'
-- Equation name is '_LC3_C5', type is buried
_LC3_C5 = LCELL( _EQ012);
_EQ012 = _LC4_C5 & !S4
# S3 & !S4
# S5;
-- Node name is '|BMQ1:26|:379'
-- Equation name is '_LC2_C5', type is buried
_LC2_C5 = LCELL( _EQ013);
_EQ013 = _LC3_C5 & !S6 & !S8
# S7 & !S8;
-- Node name is '|BMQ1:26|~410~1'
-- Equation name is '_LC1_C8', type is buried
-- synthesized logic cell
_LC1_C8 = LCELL( _EQ014);
_EQ014 = S8
# S9;
-- Node name is '|BMQ1:26|:427'
-- Equation name is '_LC4_C4', type is buried
_LC4_C4 = LCELL( _EQ015);
_EQ015 = !_LC1_B1 & _LC4_C4
# _LC1_B1 & _LC1_C8
# _LC1_B1 & _LC2_C2;
-- Node name is '|BMQ1:26|:433'
-- Equation name is '_LC5_C2', type is buried
_LC5_C2 = LCELL( _EQ016);
_EQ016 = !_LC1_B1 & _LC5_C2
# _LC1_B1 & _LC1_C2 & !_LC1_C8;
-- Node name is '|BMQ1:26|:439'
-- Equation name is '_LC7_C2', type is buried
_LC7_C2 = LCELL( _EQ017);
_EQ017 = !_LC1_B1 & _LC7_C2
# _LC1_B1 & !_LC1_C8 & _LC4_C2;
-- Node name is '|BMQ1:26|:445'
-- Equation name is '_LC1_C5', type is buried
_LC1_C5 = LCELL( _EQ018);
_EQ018 = !_LC1_B1 & _LC1_C5
# _LC1_B1 & _LC2_C5
# _LC1_B1 & S9;
-- Node name is '|BMQ1:26|:451'
-- Equation name is '_LC7_C4', type is buried
_LC7_C4 = LCELL( _EQ019);
_EQ019 = !_LC1_B1 & _LC7_C4
# _LC1_B1 & _LC1_C8
# _LC1_B1 & !_LC2_C2;
-- Node name is '|CNT3:3|:3'
-- Equation name is '_LC6_C4', type is buried
_LC6_C4 = DFFE( _EQ020, _LC7_C4, VCC, VCC, VCC);
_EQ020 = !_LC1_B1 & _LC6_C4
# !_LC5_C4 & _LC6_C4
# _LC1_B1 & _LC5_C4 & !_LC6_C4;
-- Node name is '|CNT3:3|:5'
-- Equation name is '_LC5_C4', type is buried
_LC5_C4 = DFFE( _EQ021, _LC7_C4, VCC, VCC, VCC);
_EQ021 = !_LC1_B1 & _LC5_C4
# _LC1_B1 & !_LC5_C4;
-- Node name is '|CNT31:2|:3'
-- Equation name is '_LC1_B5', type is buried
_LC1_B5 = DFFE( _EQ022, _LC1_C4, _LC1_B1, VCC, VCC);
_EQ022 = !_LC2_B5 & _LC3_B5;
-- Node name is '|CNT31:2|:5'
-- Equation name is '_LC3_B5', type is buried
_LC3_B5 = DFFE( _EQ023, _LC1_C4, _LC1_B1, VCC, VCC);
_EQ023 = _LC2_B5 & !_LC3_B5;
-- Node name is '|CNT31:2|:7'
-- Equation name is '_LC2_B5', type is buried
_LC2_B5 = DFFE( _EQ024, _LC1_C4, _LC1_B1, VCC, VCC);
_EQ024 = !_LC2_B5 & !_LC3_B5;
-- Node name is '|ICONTROL:1|:15' = '|ICONTROL:1|sp'
-- Equation name is '_LC6_B1', type is buried
_LC6_B1 = DFFE( _EQ025, GLOBAL( CLK), !i_setup, VCC, VCC);
_EQ025 = !_LC1_B8 & !_LC1_B12 & _LC4_B1 & !_LC5_B12;
-- Node name is '|ICONTROL:1|st~1'
-- Equation name is '_LC2_B12', type is buried
_LC2_B12 = DFFE( _EQ026, GLOBAL( CLK), !i_setup, VCC, VCC);
_EQ026 = iopen & _LC7_B12
# _LC2_B12 & !setup;
-- Node name is '|ICONTROL:1|st~2'
-- Equation name is '_LC4_B12', type is buried
_LC4_B12 = DFFE( _EQ027, GLOBAL( CLK), !i_setup, VCC, VCC);
_EQ027 = !iopen & _LC7_B12
# iopen & !_LC1_B5 & _LC3_B1;
-- Node name is '|ICONTROL:1|st~3'
-- Equation name is '_LC1_B8', type is buried
_LC1_B8 = DFFE( _EQ028, GLOBAL( CLK), !i_setup, VCC, VCC);
_EQ028 = _LC1_B8 & !setup
# iopen & _LC1_B12;
-- Node name is '|ICONTROL:1|st~4'
-- Equation name is '_LC1_B12', type is buried
_LC1_B12 = DFFE( _EQ029, GLOBAL( CLK), !i_setup, VCC, VCC);
_EQ029 = _LC1_B5 & _LC5_B12
# !_LC6_B12 & !setup;
-- Node name is '|ICONTROL:1|st~5'
-- Equation name is '_LC3_B1', type is buried
_LC3_B1 = DFFE( _EQ030, GLOBAL( CLK), !i_setup, VCC, VCC);
_EQ030 = !_LC5_B1 & !setup
# !_LC4_B1 & START;
-- Node name is '|ICONTROL:1|st~6'
-- Equation name is '_LC4_B1', type is buried
_LC4_B1 = DFFE( _EQ031, GLOBAL( CLK), !i_setup, VCC, VCC);
_EQ031 = _LC4_B1 & _LC7_B1
# _LC4_B1 & !setup
# _LC7_B1 & START
# !setup & START;
-- Node name is '|ICONTROL:1|:8'
-- Equation name is '_LC1_B1', type is buried
_LC1_B1 = DFFE( _EQ032, GLOBAL( CLK), !i_setup, VCC, VCC);
_EQ032 = _LC1_B12 & _LC4_B1
# _LC4_B1 & _LC5_B12;
-- Node name is '|ICONTROL:1|:10'
-- Equation name is '_LC8_B1', type is buried
_LC8_B1 = DFFE( _EQ033, GLOBAL( CLK), !i_setup, VCC, VCC);
_EQ033 = _LC1_B8 & !_LC1_B12 & !_LC3_B1 & _LC4_B1;
-- Node name is '|ICONTROL:1|:12'
-- Equation name is '_LC2_B1', type is buried
_LC2_B1 = DFFE( _EQ034, GLOBAL( CLK), !i_setup, VCC, VCC);
_EQ034 = !_LC1_B8 & !_LC1_B12 & !_LC3_B1 & _LC4_B1;
-- Node name is '|ICONTROL:1|~310~1'
-- Equation name is '_LC5_B1', type is buried
-- synthesized logic cell
!_LC5_B1 = _LC5_B1~NOT;
_LC5_B1~NOT = LCELL( _EQ035);
_EQ035 = !iopen & !_LC1_B5 & _LC3_B1;
-- Node name is '|ICONTROL:1|~318~1'
-- Equation name is '_LC6_B12', type is buried
-- synthesized logic cell
!_LC6_B12 = _LC6_B12~NOT;
_LC6_B12~NOT = LCELL( _EQ036);
_EQ036 = !iopen & _LC1_B12;
-- Node name is '|ICONTROL:1|~331~1'
-- Equation name is '_LC5_B12', type is buried
-- synthesized logic cell
_LC5_B12 = LCELL( _EQ037);
_EQ037 = _LC3_B1
# _LC4_B12;
-- Node name is '|ICONTROL:1|~332~1'
-- Equation name is '_LC7_B12', type is buried
-- synthesized logic cell
_LC7_B12 = LCELL( _EQ038);
_EQ038 = !_LC1_B5 & _LC4_B12 & !setup;
-- Node name is '|ICONTROL:1|~337~1'
-- Equation name is '_LC3_B12', type is buried
-- synthesized logic cell
_LC3_B12 = LCELL( _EQ039);
_EQ039 = !_LC1_B8 & !_LC2_B12 & !_LC4_B12
# _LC1_B5 & !_LC1_B8 & !_LC2_B12;
-- Node name is '|ICONTROL:1|~337~2'
-- Equation name is '_LC7_B1', type is buried
-- synthesized logic cell
_LC7_B1 = LCELL( _EQ040);
_EQ040 = !_LC1_B12 & _LC3_B12 & _LC5_B1
# iopen & _LC3_B12 & _LC5_B1;
-- Node name is '|ICONTROL:1|:348'
-- Equation name is '_LC1_C3', type is buried
_LC1_C3 = LCELL( _EQ041);
_EQ041 = CLK1 & _LC6_B1;
Project Information e:\zhu1\mimasuo1.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 18,485K
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