📄 mimasuo1.rpt
字号:
1 - - - -- INPUT G 0 0 0 0 CLK
43 - - - -- INPUT 0 0 0 1 CLK1
49 - - - 16 INPUT 0 0 0 6 iopen
50 - - - 17 INPUT 0 0 0 10 i_setup
44 - - - -- INPUT 0 0 0 6 setup
2 - - - -- INPUT 0 0 0 2 START
28 - - C -- INPUT 0 0 0 3 S0
29 - - C -- INPUT 0 0 0 3 S1
30 - - C -- INPUT 0 0 0 3 S2
35 - - - 06 INPUT 0 0 0 3 S3
36 - - - 07 INPUT 0 0 0 4 S4
37 - - - 09 INPUT 0 0 0 4 S5
38 - - - 10 INPUT 0 0 0 2 S6
39 - - - 11 INPUT 0 0 0 2 S7
47 - - - 14 INPUT 0 0 0 2 S8
48 - - - 15 INPUT 0 0 0 2 S9
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: e:\zhu1\mimasuo1.rpt
mimasuo1
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
25 - - B -- OUTPUT 0 1 0 0 GREEN
27 - - C -- OUTPUT 0 1 0 0 JBAO
22 - - B -- OUTPUT 0 1 0 0 RED
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\zhu1\mimasuo1.rpt
mimasuo1
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 8 - C 04 AND2 s 0 4 0 1 |BJQ1:5|~92~1
- 2 - C 04 AND2 s 0 3 0 1 |BJQ1:5|~141~1
- 3 - C 04 OR2 s 0 4 0 1 |BJQ1:5|~141~2
- 1 - C 04 OR2 0 4 0 3 |BJQ1:5|:141
- 2 - C 02 AND2 2 2 0 2 |BMQ1:26|:274
- 8 - C 02 AND2 4 0 0 2 |BMQ1:26|:298
- 3 - C 02 AND2 s ! 2 0 0 3 |BMQ1:26|~305~1
- 1 - C 02 OR2 2 2 0 1 |BMQ1:26|:305
- 6 - C 02 OR2 4 0 0 1 |BMQ1:26|:326
- 4 - C 02 OR2 2 2 0 1 |BMQ1:26|:338
- 4 - C 05 OR2 3 0 0 1 |BMQ1:26|:361
- 3 - C 05 OR2 3 1 0 1 |BMQ1:26|:365
- 2 - C 05 OR2 3 1 0 1 |BMQ1:26|:379
- 1 - C 08 OR2 s 2 0 0 4 |BMQ1:26|~410~1
- 4 - C 04 OR2 0 3 0 2 |BMQ1:26|:427
- 5 - C 02 OR2 0 3 0 2 |BMQ1:26|:433
- 7 - C 02 OR2 0 3 0 2 |BMQ1:26|:439
- 1 - C 05 OR2 1 2 0 2 |BMQ1:26|:445
- 7 - C 04 OR2 0 3 0 2 |BMQ1:26|:451
- 6 - C 04 DFFE 0 3 0 2 |CNT3:3|:3
- 5 - C 04 DFFE 0 2 0 3 |CNT3:3|:5
- 1 - B 05 DFFE 0 4 0 5 |CNT31:2|:3
- 3 - B 05 DFFE 0 3 0 2 |CNT31:2|:5
- 2 - B 05 DFFE 0 3 0 2 |CNT31:2|:7
- 2 - B 12 DFFE + 3 1 0 1 |ICONTROL:1|st~1
- 4 - B 12 DFFE + 2 3 0 3 |ICONTROL:1|st~2
- 1 - B 08 DFFE + 3 1 0 4 |ICONTROL:1|st~3
- 1 - B 12 DFFE + 2 3 0 7 |ICONTROL:1|st~4
- 3 - B 01 DFFE + 3 2 0 5 |ICONTROL:1|st~5
- 4 - B 01 DFFE + 3 1 0 5 |ICONTROL:1|st~6
- 1 - B 01 DFFE + 1 3 0 10 |ICONTROL:1|:8
- 8 - B 01 DFFE + 1 4 1 0 |ICONTROL:1|:10
- 2 - B 01 DFFE + 1 4 1 0 |ICONTROL:1|:12
- 6 - B 01 DFFE + 1 4 0 1 |ICONTROL:1|sp (|ICONTROL:1|:15)
- 5 - B 01 AND2 s ! 1 2 0 2 |ICONTROL:1|~310~1
- 6 - B 12 AND2 s ! 1 1 0 1 |ICONTROL:1|~318~1
- 5 - B 12 OR2 s 0 2 0 3 |ICONTROL:1|~331~1
- 7 - B 12 AND2 s 1 2 0 2 |ICONTROL:1|~332~1
- 3 - B 12 OR2 s 0 4 0 1 |ICONTROL:1|~337~1
- 7 - B 01 OR2 s 1 3 0 1 |ICONTROL:1|~337~2
- 1 - C 03 AND2 1 1 1 0 |ICONTROL:1|:348
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: e:\zhu1\mimasuo1.rpt
mimasuo1
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 2/ 96( 2%) 10/ 48( 20%) 0/ 48( 0%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
C: 5/ 96( 5%) 13/ 48( 27%) 0/ 48( 0%) 3/16( 18%) 1/16( 6%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
07: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
10: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
11: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
15: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
16: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
17: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\zhu1\mimasuo1.rpt
mimasuo1
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 10 CLK
LCELL 3 |BJQ1:5|:141
LCELL 3 |BMQ1:26|:451
Device-Specific Information: e:\zhu1\mimasuo1.rpt
mimasuo1
** CLEAR SIGNALS **
Type Fan-out Name
DFF 10 |ICONTROL:1|:8
INPUT 10 i_setup
Device-Specific Information: e:\zhu1\mimasuo1.rpt
mimasuo1
** EQUATIONS **
CLK : INPUT;
CLK1 : INPUT;
iopen : INPUT;
i_setup : INPUT;
setup : INPUT;
START : INPUT;
S0 : INPUT;
S1 : INPUT;
S2 : INPUT;
S3 : INPUT;
S4 : INPUT;
S5 : INPUT;
S6 : INPUT;
S7 : INPUT;
S8 : INPUT;
S9 : INPUT;
-- Node name is 'GREEN'
-- Equation name is 'GREEN', type is output
GREEN = _LC8_B1;
-- Node name is 'JBAO'
-- Equation name is 'JBAO', type is output
JBAO = _LC1_C3;
-- Node name is 'RED'
-- Equation name is 'RED', type is output
RED = _LC2_B1;
-- Node name is '|BJQ1:5|~92~1'
-- Equation name is '_LC8_C4', type is buried
-- synthesized logic cell
_LC8_C4 = LCELL( _EQ001);
_EQ001 = !_LC1_C5 & !_LC4_C4 & !_LC5_C4 & _LC7_C2;
-- Node name is '|BJQ1:5|~141~1'
-- Equation name is '_LC2_C4', type is buried
-- synthesized logic cell
_LC2_C4 = LCELL( _EQ002);
_EQ002 = _LC1_C5 & !_LC5_C2 & _LC5_C4;
-- Node name is '|BJQ1:5|~141~2'
-- Equation name is '_LC3_C4', type is buried
-- synthesized logic cell
_LC3_C4 = LCELL( _EQ003);
_EQ003 = _LC2_C4 & _LC4_C4 & _LC6_C4 & !_LC7_C2
# _LC2_C4 & !_LC4_C4 & !_LC6_C4 & _LC7_C2;
-- Node name is '|BJQ1:5|:141'
-- Equation name is '_LC1_C4', type is buried
_LC1_C4 = LCELL( _EQ004);
_EQ004 = _LC3_C4
# _LC5_C2 & _LC6_C4 & _LC8_C4;
-- Node name is '|BMQ1:26|:274'
-- Equation name is '_LC2_C2', type is buried
_LC2_C2 = LCELL( _EQ005);
_EQ005 = !_LC3_C2 & _LC8_C2 & !S4 & !S5;
-- Node name is '|BMQ1:26|:298'
-- Equation name is '_LC8_C2', type is buried
_LC8_C2 = LCELL( _EQ006);
_EQ006 = !S0 & !S1 & !S2 & !S3;
-- Node name is '|BMQ1:26|~305~1'
-- Equation name is '_LC3_C2', type is buried
-- synthesized logic cell
!_LC3_C2 = _LC3_C2~NOT;
_LC3_C2~NOT = LCELL( _EQ007);
_EQ007 = !S6 & !S7;
-- Node name is '|BMQ1:26|:305'
-- Equation name is '_LC1_C2', type is buried
_LC1_C2 = LCELL( _EQ008);
_EQ008 = S5
# S4
# _LC3_C2
# _LC8_C2;
-- Node name is '|BMQ1:26|:326'
-- Equation name is '_LC6_C2', type is buried
_LC6_C2 = LCELL( _EQ009);
_EQ009 = !S0 & !S1
# S3
# S2;
-- Node name is '|BMQ1:26|:338'
-- Equation name is '_LC4_C2', type is buried
_LC4_C2 = LCELL( _EQ010);
_EQ010 = _LC6_C2 & !S4 & !S5
# _LC3_C2;
-- Node name is '|BMQ1:26|:361'
-- Equation name is '_LC4_C5', type is buried
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -