icontrol.rpt

VHDL的课程设计

** BURIED LOGIC **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
 (39)    19    B       DFFE   +  t        1      0   1    5    3    3    4  st~1
 (40)    18    B       DFFE   +  t        0      0   0    4    3    3    4  st~2
 (41)    17    B       DFFE   +  t        0      0   0    4    3    3    4  st~3
 (37)    21    B       DFFE   +  t        0      0   0    1    3    1    0  sp (:15)


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                              e:\zhu1\icontrol.rpt
icontrol

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'B':

                         Logic cells placed in LAB 'B'
        +--------------- LC24 en
        | +------------- LC23 green
        | | +----------- LC22 jibao
        | | | +--------- LC20 red
        | | | | +------- LC19 st~1
        | | | | | +----- LC18 st~2
        | | | | | | +--- LC17 st~3
        | | | | | | | +- LC21 sp
        | | | | | | | | 
        | | | | | | | |   Other LABs fed by signals
        | | | | | | | |   that feed LAB 'B'
LC      | | | | | | | | | A B |     Logic cells that feed LAB 'B':
LC19 -> * * - * * * * * | - * | <-- st~1
LC18 -> * * - * * * * * | - * | <-- st~2
LC17 -> * * - * * * * * | - * | <-- st~3
LC21 -> - - * - - - - - | - * | <-- sp

Pin
43   -> - - - - - - - - | - - | <-- clk
4    -> - - * - - - - - | - * | <-- clk1
6    -> - - - - * * * - | - * | <-- iopen
7    -> * * - * * * * * | - * | <-- i_set
9    -> - - - - * * * - | - * | <-- result
8    -> - - - - * * * - | - * | <-- set
5    -> - - - - * - - - | - * | <-- start


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                              e:\zhu1\icontrol.rpt
icontrol

** EQUATIONS **

clk      : INPUT;
clk1     : INPUT;
iopen    : INPUT;
i_set    : INPUT;
result   : INPUT;
set      : INPUT;
start    : INPUT;

-- Node name is 'en' = ':8' 
-- Equation name is 'en', type is output 
 en      = DFFE( _EQ001 $ !st~3, GLOBAL( clk), !i_set,  VCC,  VCC);
  _EQ001 = !st~1 & !st~2 & !st~3;

-- Node name is 'green' = ':10' 
-- Equation name is 'green', type is output 
 green   = DFFE( _EQ002 $  GND, GLOBAL( clk), !i_set,  VCC,  VCC);
  _EQ002 = !st~1 & !st~2 &  st~3;

-- Node name is 'jibao' 
-- Equation name is 'jibao', location is LC022, type is output.
 jibao   = LCELL( _EQ003 $  GND);
  _EQ003 =  clk1 &  sp;

-- Node name is 'red' = ':12' 
-- Equation name is 'red', type is output 
 red     = DFFE( _EQ004 $  st~3, GLOBAL( clk), !i_set,  VCC,  VCC);
  _EQ004 =  st~1 &  st~2 & !st~3
         # !st~1 & !st~2 &  st~3;

-- Node name is ':15' = 'sp' 
-- Equation name is 'sp', location is LC021, type is buried.
sp       = DFFE( _EQ005 $  st~3, GLOBAL( clk), !i_set,  VCC,  VCC);
  _EQ005 = !st~1 & !st~2 &  st~3;

-- Node name is 'st~1' 
-- Equation name is 'st~1', location is LC019, type is buried.
st~1     = DFFE( _EQ006 $  GND, GLOBAL( clk), !i_set,  VCC,  VCC);
  _EQ006 =  iopen & !result &  st~1 & !st~2 & !st~3
         # !set &  st~1 & !st~2 &  st~3
         # !result & !set &  st~1 & !st~3
         #  start & !st~1 & !st~2 & !st~3;

-- Node name is 'st~2' 
-- Equation name is 'st~2', location is LC018, type is buried.
st~2     = DFFE( _EQ007 $  GND, GLOBAL( clk), !i_set,  VCC,  VCC);
  _EQ007 =  iopen &  st~1 & !st~2 & !st~3
         # !iopen & !set &  st~2 & !st~3
         #  result &  st~1 & !st~3;

-- Node name is 'st~3' 
-- Equation name is 'st~3', location is LC017, type is buried.
st~3     = DFFE( _EQ008 $  GND, GLOBAL( clk), !i_set,  VCC,  VCC);
  _EQ008 =  iopen & !result & !set &  st~2 & !st~3
         #  iopen & !st~1 &  st~2 & !st~3
         # !set & !st~2 &  st~3;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                                       e:\zhu1\icontrol.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:00


Memory Allocated
-----------------

Peak memory allocated during compilation  = 12,506K