xzq.vhd

VHDL的课程设计

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity xzq is
port(sel    :in  std_logic_vector(1 downto 0);
     dout   :out  std_logic_vector(3 downto 0));
end xzq;
architecture behav of xzq is
begin
process(sel)
begin
if(sel="01")then
dout<="0011";
elsif(sel="10")then
dout<="0110";
elsif(sel="11")then
dout<="1001";
else
dout<="1111";
end if;
end process;
end behav;