bmq1.rpt

VHDL的课程设计

Pin
4    -> * * * * * - - - - - * * * * * | - * | <-- en
16   -> * - - - - * * * * * * * - - * | - * | <-- s0
14   -> * - - - - * * * * * * * - - * | - * | <-- s1
13   -> * - - - - * * * * * * * - - * | - * | <-- s2
12   -> * - - - - * * * * * * * - - * | - * | <-- s3
11   -> * - - - - * * * * * * * - - * | - * | <-- s4
9    -> * - - - - * * * * * * * - - * | - * | <-- s5
8    -> * - - - - * * * * * * * - - * | - * | <-- s6
7    -> * - - - - * * * * * * * - - * | - * | <-- s7
6    -> * - - - - * * * * * * * - - * | - * | <-- s8
5    -> * * * * - * - - - * * * * * * | - * | <-- s9


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                                  e:\zhu1\bmq1.rpt
bmq1

** EQUATIONS **

en       : INPUT;
s0       : INPUT;
s1       : INPUT;
s2       : INPUT;
s3       : INPUT;
s4       : INPUT;
s5       : INPUT;
s6       : INPUT;
s7       : INPUT;
s8       : INPUT;
s9       : INPUT;

-- Node name is 'sor' 
-- Equation name is 'sor', location is LC026, type is output.
 sor     = LCELL( _EQ001 $  GND);
  _EQ001 =  en &  _X001
         # !en &  _LC018;
  _X001  = EXP(!s0 & !s1 & !s2 & !s3 & !s4 & !s5 & !s6 & !s7 & !s8 & !s9);

-- Node name is 'y0' 
-- Equation name is 'y0', location is LC027, type is output.
 y0      = LCELL( _EQ002 $  en);
  _EQ002 =  en & !_LC021 & !s9
         # !en &  _LC025;

-- Node name is 'y1' 
-- Equation name is 'y1', location is LC028, type is output.
 y1      = LCELL( _EQ003 $  GND);
  _EQ003 =  en &  _LC020 & !s9
         # !en &  _LC029;

-- Node name is 'y2' 
-- Equation name is 'y2', location is LC030, type is output.
 y2      = LCELL( _EQ004 $  GND);
  _EQ004 =  en &  _LC019 & !s9
         # !en &  _LC024;

-- Node name is 'y3' 
-- Equation name is 'y3', location is LC031, type is output.
 y3      = LCELL( _EQ005 $  GND);
  _EQ005 =  en &  _LC017
         # !en &  _LC023;

-- Node name is '~278~1' 
-- Equation name is '~278~1', location is LC017, type is buried.
-- synthesized logic cell 
_LC017   = LCELL( _EQ006 $  s9);
  _EQ006 = !s0 & !s1 & !s2 & !s3 & !s4 & !s5 & !s6 & !s7 & !s9
         #  s8 & !s9;

-- Node name is '~308~1' 
-- Equation name is '~308~1', location is LC019, type is buried.
-- synthesized logic cell 
_LC019   = LCELL( _EQ007 $ !s8);
  _EQ007 =  s3 & !s4 & !s5 & !s6 & !s7 & !s8
         #  s2 & !s4 & !s5 & !s6 & !s7 & !s8
         #  s1 & !s4 & !s5 & !s6 & !s7 & !s8
         #  s0 & !s4 & !s5 & !s6 & !s7 & !s8;

-- Node name is '~341~1' 
-- Equation name is '~341~1', location is LC020, type is buried.
-- synthesized logic cell 
_LC020   = LCELL( _EQ008 $ !s8);
  _EQ008 =  s1 & !s2 & !s3 & !s6 & !s7 & !s8
         #  s0 & !s2 & !s3 & !s6 & !s7 & !s8
         #  s5 & !s6 & !s7 & !s8
         #  s4 & !s6 & !s7 & !s8;

-- Node name is '~374~1' 
-- Equation name is '~374~1', location is LC021, type is buried.
-- synthesized logic cell 
_LC021   = LCELL( _EQ009 $ !s8);
  _EQ009 =  s0 & !s1 & !s3 & !s5 & !s7 & !s8
         #  s2 & !s3 & !s5 & !s7 & !s8
         #  s4 & !s5 & !s7 & !s8
         #  s6 & !s7 & !s8;

-- Node name is '~427~1~2' 
-- Equation name is '~427~1~2', location is LC022, type is buried.
-- synthesized logic cell 
_LC022   = LCELL( _EQ010 $  GND);
  _EQ010 =  _LC023 & !s0 & !s1 & !s2 & !s3 & !s4 & !s5 & !s6 & !s7
         #  _LC023 &  s8
         #  _LC023 &  s9;

-- Node name is '~427~1' 
-- Equation name is '~427~1', location is LC023, type is buried.
-- synthesized logic cell 
_LC023   = LCELL( _EQ011 $  GND);
  _EQ011 =  en & !s0 & !s1 & !s2 & !s3 & !s4 & !s5 & !s6 & !s7
         #  en &  s8
         #  en &  s9
         # !en &  _LC023
         #  _LC022;

-- Node name is '~433~1' 
-- Equation name is '~433~1', location is LC024, type is buried.
-- synthesized logic cell 
_LC024   = LCELL( _EQ012 $  GND);
  _EQ012 =  en & !s0 & !s1 & !s2 & !s3 & !s8 & !s9
         #  en & !s8 & !s9 &  _X002
         # !en &  _LC024
         #  _LC024 & !s0 & !s1 & !s2 & !s3 & !s8 & !s9
         #  _LC024 & !s8 & !s9 &  _X002;
  _X002  = EXP(!s4 & !s5 & !s6 & !s7);

-- Node name is '~439~1' 
-- Equation name is '~439~1', location is LC029, type is buried.
-- synthesized logic cell 
_LC029   = LCELL( _EQ013 $  GND);
  _EQ013 =  en &  _LC020 & !s9
         # !en &  _LC029
         #  _LC020 &  _LC029 & !s9;

-- Node name is '~445~1' 
-- Equation name is '~445~1', location is LC025, type is buried.
-- synthesized logic cell 
_LC025   = LCELL( _EQ014 $  VCC);
  _EQ014 =  en & !_LC021 & !s9
         # !en & !_LC025
         # !_LC021 & !_LC025 & !s9;

-- Node name is '~451~1' 
-- Equation name is '~451~1', location is LC018, type is buried.
-- synthesized logic cell 
_LC018   = LCELL( _EQ015 $  GND);
  _EQ015 =  en &  _X001
         # !en &  _LC018
         #  _LC018 &  _X001;
  _X001  = EXP(!s0 & !s1 & !s2 & !s3 & !s4 & !s5 & !s6 & !s7 & !s8 & !s9);



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                                           e:\zhu1\bmq1.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:00


Memory Allocated
-----------------

Peak memory allocated during compilation  = 12,705K