hello.fit.talkback.xml

DE2板上的hello程序,实现在8个七段译码器上循环显示hello

<!--
This XML file (created on Mon Jun 25 14:11:43 2007) contains limited information
from the compilation of logic designs using Quartus II software (BUT NOT THE
LOGIC DESIGN FILES) that will be transmitted to Altera Corporation through
operation of the "TalkBack" feature.  To enable/disable this feature, run
qtb_install.exe located in your quartus/bin folder.  For more information, go
to license.txt.
-->
<talkback>
<ver>6.0</ver>
<schema>quartus_version_6.0_build_178.xsd</schema>
<license>
	<host_id>00e04cef65bf</host_id>
	<nic_id>00e04cef65bf</nic_id>
	<cdrive_id>48e51b1f</cdrive_id>
</license>
<tool>
	<name>Quartus II</name>
	<version>6.0</version>
	<build>Build 178</build>
	<binary_type>32</binary_type>
	<module>quartus_fit</module>
	<edition>Full Version</edition>
	<eval>Licensed</eval>
	<compilation_end_time>Mon Jun 25 14:11:43 2007</compilation_end_time>
</tool>
<machine>
	<os>Windows XP</os>
	<cpu>
		<proc_count>1</proc_count>
		<cpu_freq units="MHz">2300</cpu_freq>
	</cpu>
	<ram units="MB">447</ram>
</machine>
<project>D:/altera/程序/Hello/Hello</project>
<revision>Hello</revision>
<compilation_summary>
	<flow_status>Successful - Mon Jun 25 14:11:43 2007</flow_status>
	<quartus_ii_version>6.0 Build 178 04/27/2006 SJ Web Edition</quartus_ii_version>
	<revision_name>Hello</revision_name>
	<top_level_entity_name>Hello</top_level_entity_name>
	<family>Cyclone II</family>
	<device>EP2C35F672C6</device>
	<timing_models>Final</timing_models>
	<met_timing_requirements>N/A</met_timing_requirements>
	<total_logic_elements>45 / 33,216 ( &lt; 1 % )</total_logic_elements>
	<total_registers>0</total_registers>
	<total_pins>74 / 475 ( 16 % )</total_pins>
	<total_virtual_pins>0</total_virtual_pins>
	<total_memory_bits>0 / 483,840 ( 0 % )</total_memory_bits>
	<embedded_multiplier_9_bit_elements>0 / 70 ( 0 % )</embedded_multiplier_9_bit_elements>
	<total_plls>0 / 4 ( 0 % )</total_plls>
</compilation_summary>
<resource_usage_summary>
	<rsc name="Total logic elements" util="1" max=" 33216 " type="int">45 </rsc>
	<rsc name="-- Combinational with no register" type="int">45</rsc>
	<rsc name="-- Register only" type="int">0</rsc>
	<rsc name="-- Combinational with a register" type="int">0</rsc>
	<rsc name="Logic element usage by number of LUT inputs" type="text"></rsc>
	<rsc name="-- 4 input functions" type="int">10</rsc>
	<rsc name="-- 3 input functions" type="int">25</rsc>
	<rsc name="-- &lt;=2 input functions" type="int">10</rsc>
	<rsc name="-- Register only" type="int">0</rsc>
	<rsc name="Logic elements by mode" type="text"></rsc>
	<rsc name="-- normal mode" type="int">45</rsc>
	<rsc name="-- arithmetic mode" type="int">0</rsc>
	<rsc name="Total registers" util="0" max=" 33216 " type="int">0 </rsc>
	<rsc name="Total LABs" util="1" max=" 2076 " type="int">3 </rsc>
	<rsc name="User inserted logic elements" type="int">0</rsc>
	<rsc name="Virtual pins" type="int">0</rsc>
	<rsc name="I/O pins" util="16" max=" 475 " type="int">74 </rsc>
	<rsc name="-- Clock pins" util="100" max=" 8 " type="int">8 </rsc>
	<rsc name="Global signals" type="int">0</rsc>
	<rsc name="M4Ks" util="0" max=" 105 " type="int">0 </rsc>
	<rsc name="Total memory bits" util="0" max=" 483840 " type="int">0 </rsc>
	<rsc name="Total RAM block bits" util="0" max=" 483840 " type="int">0 </rsc>
	<rsc name="Embedded Multiplier 9-bit elements" util="0" max=" 70 " type="int">0 </rsc>
	<rsc name="PLLs" util="0" max=" 4 " type="int">0 </rsc>
	<rsc name="Global clocks" util="0" max=" 16 " type="int">0 </rsc>
	<rsc name="Maximum fan-out node" type="text">mux51a:M0|s_machine:u5|sout[1]~245</rsc>
	<rsc name="Maximum fan-out" type="int">31</rsc>
	<rsc name="Highest non-global fan-out signal" type="text">mux51a:M0|s_machine:u5|sout[1]~245</rsc>
	<rsc name="Highest non-global fan-out" type="int">31</rsc>
	<rsc name="Total fan-out" type="int">191</rsc>
	<rsc name="Average fan-out" type="float">1.57</rsc>
</resource_usage_summary>
<non_global_high_fan_out_signals>
	<row>
		<name>mux51a:M0|mux21b:u4|mux21a:u3|m~25</name>
		<fan_out>1</fan_out>
	</row>
	<row>
		<name>mux51a:M0|mux21b:u4|mux21a:u3|m~26</name>
		<fan_out>1</fan_out>
	</row>
	<row>
		<name>mux51a:M0|mux21b:u4|mux21a:u3|m~27</name>
		<fan_out>3</fan_out>
	</row>
	<row>
		<name>mux51a:M0|mux21b:u4|mux21a:u1|m~26</name>
		<fan_out>1</fan_out>
	</row>
	<row>
		<name>mux51a:M0|mux21b:u4|mux21a:u1|m~27</name>
		<fan_out>1</fan_out>
	</row>
	<row>
		<name>mux51a:M0|mux21b:u4|mux21a:u1|m~28</name>
		<fan_out>3</fan_out>
	</row>
	<row>
		<name>mux51a:M0|mux21b:u4|mux21a:u2|m~25</name>
		<fan_out>1</fan_out>
	</row>
	<row>
		<name>mux51a:M0|mux21b:u4|mux21a:u2|m~26</name>
		<fan_out>1</fan_out>
	</row>
	<row>
		<name>mux51a:M0|mux21b:u4|mux21a:u2|m~27</name>
		<fan_out>3</fan_out>
	</row>
	<row>
		<name>mux51a:M0|s_machine:u5|sout[2]~243</name>
		<fan_out>28</fan_out>
	</row>
</non_global_high_fan_out_signals>
<interconnect_usage_summary>
	<rsc name="Local interconnects" util="1" max=" 33216 " type="int">10 </rsc>
	<rsc name="Block interconnects" util="1" max=" 94460 " type="int">73 </rsc>
	<rsc name="R4 interconnects" util="1" max=" 81294 " type="int">183 </rsc>
	<rsc name="R24 interconnects" util="1" max=" 3091 " type="int">46 </rsc>
	<rsc name="C4 interconnects" util="1" max=" 60840 " type="int">79 </rsc>
	<rsc name="C16 interconnects" util="1" max=" 3315 " type="int">23 </rsc>
	<rsc name="Global clocks" util="0" max=" 16 " type="int">0 </rsc>
	<rsc name="Direct links" util="1" max=" 94460 " type="int">8 </rsc>
</interconnect_usage_summary>
<mep_data>
	<command_line>quartus_fit --read_settings_files=off --write_settings_files=off Hello -c Hello</command_line>
</mep_data>
<software_data>
	<smart_recompile>off</smart_recompile>
</software_data>
<messages>
	<warning>Warning: Found 56 output pins without output pin load capacitance assignment</warning>
	<warning>Warning: Ignored locations or region assignments to the following nodes</warning>
	<warning>Warning: Node &quot;VGA_VS&quot; is assigned to location or region, but does not exist in design</warning>
	<warning>Warning: Node &quot;VGA_SYNC&quot; is assigned to location or region, but does not exist in design</warning>
	<warning>Warning: Node &quot;VGA_R[9]&quot; is assigned to location or region, but does not exist in design</warning>
	<info>Info: Generated suppressed messages file D:/altera/程序/Hello/Hello.fit.smsg</info>
	<info>Info: Quartus II Fitter was successful. 0 errors, 353 warnings</info>
	<info>Info: Elapsed time: 00:00:11</info>
	<info>Info: Processing ended: Mon Jun 25 14:11:43 2007</info>
	<info>Info: Delay annotation completed successfully</info>
</messages>
<fitter_settings>
	<row>
		<option>Device</option>
		<setting>EP2C35F672C6</setting>
	</row>
	<row>
		<option>Use smart compilation</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Router Timing Optimization Level</option>
		<setting>Normal</setting>
		<default_value>Normal</default_value>
	</row>
	<row>
		<option>Placement Effort Multiplier</option>
		<setting>1.0</setting>
		<default_value>1.0</default_value>
	</row>
	<row>
		<option>Router Effort Multiplier</option>
		<setting>1.0</setting>
		<default_value>1.0</default_value>
	</row>
	<row>
		<option>Optimize Hold Timing</option>
		<setting>IO Paths and Minimum TPD Paths</setting>
		<default_value>IO Paths and Minimum TPD Paths</default_value>
	</row>
	<row>
		<option>Optimize Fast-Corner Timing</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>PowerPlay Power Optimization</option>
		<setting>Normal compilation</setting>
		<default_value>Normal compilation</default_value>
	</row>
	<row>
		<option>Optimize Timing</option>
		<setting>Normal compilation</setting>
		<default_value>Normal compilation</default_value>
	</row>
	<row>
		<option>Optimize IOC Register Placement for Timing</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Limit to One Fitting Attempt</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Final Placement Optimizations</option>
		<setting>Automatically</setting>
		<default_value>Automatically</default_value>
	</row>
	<row>
		<option>Fitter Aggressive Routability Optimizations</option>
		<setting>Automatically</setting>
		<default_value>Automatically</default_value>
	</row>
	<row>
		<option>Fitter Initial Placement Seed</option>
		<setting>1</setting>
		<default_value>1</default_value>
	</row>
	<row>
		<option>PCI I/O</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Weak Pull-Up Resistor</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Enable Bus-Hold Circuitry</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Auto Global Memory Control Signals</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Auto Packed Registers -- Stratix II/Cyclone II</option>
		<setting>Auto</setting>
		<default_value>Auto</default_value>
	</row>
	<row>
		<option>Auto Delay Chains</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Auto Merge PLLs</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Ignore PLL Mode When Merging PLLs</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Fitter Effort</option>
		<setting>Auto Fit</setting>
		<default_value>Auto Fit</default_value>
	</row>
	<row>
		<option>Physical Synthesis Effort Level</option>
		<setting>Normal</setting>
		<default_value>Normal</default_value>
	</row>
	<row>
		<option>Auto Global Clock</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Auto Global Register Control Signals</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Always Enable Input Buffers</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
</fitter_settings>
<fitter_device_options>
	<row>
		<option>Enable user-supplied start-up clock (CLKUSR)</option>
		<setting>Off</setting>
	</row>
	<row>
		<option>Enable device-wide reset (DEV_CLRn)</option>
		<setting>Off</setting>
	</row>
	<row>
		<option>Enable device-wide output enable (DEV_OE)</option>
		<setting>Off</setting>
	</row>
	<row>
		<option>Enable INIT_DONE output</option>
		<setting>Off</setting>
	</row>
	<row>
		<option>Configuration scheme</option>
		<setting>Active Serial</setting>
	</row>
	<row>
		<option>Error detection CRC</option>
		<setting>Off</setting>
	</row>
	<row>
		<option>Reserve nCEO pin after configuration</option>
		<setting>As output driving ground</setting>
	</row>
	<row>
		<option>Reserve all unused pins</option>
		<setting>As output driving ground</setting>
	</row>
	<row>
		<option>Base pin-out file on sameframe device</option>
		<setting>Off</setting>
	</row>
</fitter_device_options>
<input_pins>
	<row>
		<name>SW[0]</name>
		<pin__>N25</pin__>
		<i_o_bank>5</i_o_bank>
		<x_coordinate>65</x_coordinate>
		<y_coordinate>19</y_coordinate>
		<cell_number>0</cell_number>
		<combinational_fan_out>2</combinational_fan_out>
		<registered_fan_out>0</registered_fan_out>
		<global>no</global>
		<input_register>no</input_register>
		<power_up_high>no</power_up_high>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<termination>Off</termination>
		<location_assigned_by>User</location_assigned_by>
	</row>
	<row>
		<name>SW[10]</name>
		<pin__>N1</pin__>
		<i_o_bank>2</i_o_bank>
		<x_coordinate>0</x_coordinate>
		<y_coordinate>18</y_coordinate>
		<cell_number>1</cell_number>
		<combinational_fan_out>1</combinational_fan_out>
		<registered_fan_out>0</registered_fan_out>
		<global>no</global>
		<input_register>no</input_register>
		<power_up_high>no</power_up_high>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<termination>Off</termination>
		<location_assigned_by>User</location_assigned_by>
	</row>
	<row>
		<name>SW[11]</name>
		<pin__>P1</pin__>
		<i_o_bank>1</i_o_bank>
		<x_coordinate>0</x_coordinate>
		<y_coordinate>18</y_coordinate>
		<cell_number>3</cell_number>
		<combinational_fan_out>1</combinational_fan_out>
		<registered_fan_out>0</registered_fan_out>
		<global>no</global>
		<input_register>no</input_register>
		<power_up_high>no</power_up_high>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<termination>Off</termination>
		<location_assigned_by>User</location_assigned_by>
	</row>
	<row>
		<name>SW[12]</name>
		<pin__>P2</pin__>
		<i_o_bank>1</i_o_bank>
		<x_coordinate>0</x_coordinate>
		<y_coordinate>18</y_coordinate>
		<cell_number>2</cell_number>
		<combinational_fan_out>1</combinational_fan_out>
		<registered_fan_out>0</registered_fan_out>
		<global>no</global>
		<input_register>no</input_register>
		<power_up_high>no</power_up_high>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>