top.msg

《设计与验证Verilog HDL》光盘内容

@TM:1141840652
@W: MT118 :"":0:0:0:-1|Paths from clock (top|CS_:f) to clock (top|OE_:r) are overconstrained because the required time of 0.01 ns is too small.  
@N: MT195 :"":0:0:0:-1|This timing report estimates place and route data. Please look at the place and route timing report for final timing..
@N: MT197 :"":0:0:0:-1|Clock constraints cover only FF-to-FF paths associated with the clock..
@N: MT204 :"":0:0:0:-1|Autoconstrain Mode is ON
@TM:1141840649
@N:  :"c:\prj\example-4-21\oe_edge\decode.v":3:7:3:12|Synthesizing module decode
@W: CL159 :"c:\prj\example-4-21\oe_edge\decode.v":5:18:5:20|M
@W: CL118 :"c:\prj\example-4-21\oe_edge\decode.v":17:2:17:3|M
@N:  :"c:\prj\example-4-21\oe_edge\read_reg.v":2:7:2:14|Synthesizing module read_reg
@N:  :"c:\prj\example-4-21\oe_edge\top.v":1:7:1:9|Synthesizing module top
@TM:1141840652
@W: BN132 :"c:\prj\example-4-21\oe_edge\top.v":16:7:16:15|M
@TM:1141840649
@W: CS148 :"c:\prj\example-4-21\oe_edge\top.v":16:7:16:15|M
@N:  :"c:\prj\example-4-21\oe_edge\write_reg.v":2:7:2:15|Synthesizing module write_reg
@N: CG179 :"c:\prj\example-4-21\oe_edge\write_reg.v":29:29:29:32|M
@N: CG179 :"c:\prj\example-4-21\oe_edge\write_reg.v":30:29:30:32|M
@N: CG179 :"c:\prj\example-4-21\oe_edge\write_reg.v":31:29:31:32|M