rs_encode_and_decode.smp_dump.txt

来自「RS编码的verilog源代码」· 文本 代码 · 共 48 行

State Machine - |rs|RSDecoder:inst1|rsdec:rsdec|MainControl:controller|state1
Name state1.st1_14 state1.st1_1 state1.st1_2 state1.st1_3 state1.st1_4 state1.st1_5 state1.st1_6 state1.st1_7 state1.st1_8 state1.st1_9 state1.st1_10 state1.st1_11 state1.st1_12 state1.st1_13 state1.st1_0 
state1.st1_0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
state1.st1_13 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 
state1.st1_12 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 
state1.st1_11 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 
state1.st1_10 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 
state1.st1_9 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 
state1.st1_8 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 
state1.st1_7 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 
state1.st1_6 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 
state1.st1_5 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 
state1.st1_4 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 
state1.st1_3 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 
state1.st1_2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 
state1.st1_1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 
state1.st1_14 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 

State Machine - |rs|RSDecoder:inst1|rsdec:rsdec|MainControl:controller|state2
Name state2.st2_11 state2.st2_1 state2.st2_2 state2.st2_3 state2.st2_4 state2.st2_5 state2.st2_6 state2.st2_7 state2.st2_8 state2.st2_9 state2.st2_10 state2.st2_0 
state2.st2_0 0 0 0 0 0 0 0 0 0 0 0 0 
state2.st2_10 0 0 0 0 0 0 0 0 0 0 1 1 
state2.st2_9 0 0 0 0 0 0 0 0 0 1 0 1 
state2.st2_8 0 0 0 0 0 0 0 0 1 0 0 1 
state2.st2_7 0 0 0 0 0 0 0 1 0 0 0 1 
state2.st2_6 0 0 0 0 0 0 1 0 0 0 0 1 
state2.st2_5 0 0 0 0 0 1 0 0 0 0 0 1 
state2.st2_4 0 0 0 0 1 0 0 0 0 0 0 1 
state2.st2_3 0 0 0 1 0 0 0 0 0 0 0 1 
state2.st2_2 0 0 1 0 0 0 0 0 0 0 0 1 
state2.st2_1 0 1 0 0 0 0 0 0 0 0 0 1 
state2.st2_11 1 0 0 0 0 0 0 0 0 0 0 1 

State Machine - |rs|RSDecoder:inst1|rsdec:rsdec|KES_block:KESblock|control:mcontrol|state
Name state.st1 state.st2 state.st3 state.st0 state.st4 
state.st0 0 0 0 0 0 
state.st3 0 0 1 1 0 
state.st2 0 1 0 1 0 
state.st1 1 0 0 1 0 
state.st4 0 0 0 1 1 

State Machine - |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|state
Name state.st0 state.st2 state.st1 
state.st0 0 0 0 
state.st1 1 0 1 
state.st2 1 1 0