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RS编码的verilog源代码

; |rs|RSEncoder:inst|Dec2Bit:E|Select~346                                                                        ; |rs|RSEncoder:inst|Dec2Bit:E|Select~346                                                                        ; combout          ;
; |rs|RSDecoder:inst1|divide5:dividea|clk_out                                                                    ; |rs|RSDecoder:inst1|divide5:dividea|clk_out                                                                    ; combout          ;
; |rs|RSDecoder:inst1|rsdec:rsdec|fifo_register:fiforeg|register5_wl:outreg|dataout[3]                           ; |rs|RSDecoder:inst1|rsdec:rsdec|fifo_register:fiforeg|register5_wl:outreg|dataout[3]                           ; regout           ;
; |rs|RSDecoder:inst1|rsdec:rsdec|CSEEblock:CSEEblock|register5_wl:erroreg|dataout[3]                            ; |rs|RSDecoder:inst1|rsdec:rsdec|CSEEblock:CSEEblock|register5_wl:erroreg|dataout[3]                            ; regout           ;
; |rs|RSDecoder:inst1|rsdec:rsdec|gfadder:adder|out[1]                                                           ; |rs|RSDecoder:inst1|rsdec:rsdec|gfadder:adder|out[1]                                                           ; combout          ;
; |rs|RSDecoder:inst1|fifo_decode:fifo_decode|wraddress[0]                                                       ; |rs|RSDecoder:inst1|fifo_decode:fifo_decode|wraddress[0]                                                       ; regout           ;
; |rs|RSDecoder:inst1|fifo_decode:fifo_decode|wraddress[1]                                                       ; |rs|RSDecoder:inst1|fifo_decode:fifo_decode|wraddress[1]                                                       ; regout           ;
; |rs|RSDecoder:inst1|fifo_decode:fifo_decode|wraddress[2]                                                       ; |rs|RSDecoder:inst1|fifo_decode:fifo_decode|wraddress[2]                                                       ; regout           ;
; |rs|RSDecoder:inst1|fifo_decode:fifo_decode|wraddress[3]                                                       ; |rs|RSDecoder:inst1|fifo_decode:fifo_decode|wraddress[3]                                                       ; regout           ;
; |rs|RSDecoder:inst1|fifo_decode:fifo_decode|wraddress[4]                                                       ; |rs|RSDecoder:inst1|fifo_decode:fifo_decode|wraddress[4]                                                       ; regout           ;
; |rs|RSDecoder:inst1|fifo_decode:fifo_decode|rdaddress[0]                                                       ; |rs|RSDecoder:inst1|fifo_decode:fifo_decode|rdaddress[0]                                                       ; regout           ;
; |rs|RSDecoder:inst1|fifo_decode:fifo_decode|rdaddress[0]                                                       ; |rs|RSDecoder:inst1|fifo_decode:fifo_decode|rdaddress[0]~942                                                   ; cout0            ;
; |rs|RSDecoder:inst1|fifo_decode:fifo_decode|rdaddress[0]                                                       ; |rs|RSDecoder:inst1|fifo_decode:fifo_decode|rdaddress[0]~942COUT1_966                                          ; cout1            ;
; |rs|RSDecoder:inst1|fifo_decode:fifo_decode|rdaddress[1]                                                       ; |rs|RSDecoder:inst1|fifo_decode:fifo_decode|rdaddress[1]                                                       ; regout           ;
; |rs|RSDecoder:inst1|fifo_decode:fifo_decode|rdaddress[1]                                                       ; |rs|RSDecoder:inst1|fifo_decode:fifo_decode|rdaddress[1]~946                                                   ; cout0            ;
; |rs|RSDecoder:inst1|fifo_decode:fifo_decode|rdaddress[1]                                                       ; |rs|RSDecoder:inst1|fifo_decode:fifo_decode|rdaddress[1]~946COUT1_967                                          ; cout1            ;
; |rs|RSDecoder:inst1|fifo_decode:fifo_decode|rdaddress[2]                                                       ; |rs|RSDecoder:inst1|fifo_decode:fifo_decode|rdaddress[2]                                                       ; regout           ;
; |rs|RSDecoder:inst1|fifo_decode:fifo_decode|rdaddress[2]                                                       ; |rs|RSDecoder:inst1|fifo_decode:fifo_decode|rdaddress[2]~950                                                   ; cout0            ;
; |rs|RSDecoder:inst1|fifo_decode:fifo_decode|rdaddress[2]                                                       ; |rs|RSDecoder:inst1|fifo_decode:fifo_decode|rdaddress[2]~950COUT1_969                                          ; cout1            ;
; |rs|RSDecoder:inst1|fifo_decode:fifo_decode|rdaddress[3]                                                       ; |rs|RSDecoder:inst1|fifo_decode:fifo_decode|rdaddress[3]                                                       ; regout           ;
; |rs|RSDecoder:inst1|fifo_decode:fifo_decode|rdaddress[3]                                                       ; |rs|RSDecoder:inst1|fifo_decode:fifo_decode|rdaddress[3]~954                                                   ; cout0            ;
; |rs|RSDecoder:inst1|fifo_decode:fifo_decode|rdaddress[3]                                                       ; |rs|RSDecoder:inst1|fifo_decode:fifo_decode|rdaddress[3]~954COUT1_971                                          ; cout1            ;
; |rs|RSDecoder:inst1|fifo_decode:fifo_decode|rdaddress[4]                                                       ; |rs|RSDecoder:inst1|fifo_decode:fifo_decode|rdaddress[4]                                                       ; regout           ;
; |rs|RSDecoder:inst1|rsdec:rsdec|fifo_register:fiforeg|register5_wl:outreg|dataout[4]                           ; |rs|RSDecoder:inst1|rsdec:rsdec|fifo_register:fiforeg|register5_wl:outreg|dataout[4]                           ; regout           ;
; |rs|RSDecoder:inst1|rsdec:rsdec|CSEEblock:CSEEblock|register5_wl:erroreg|dataout[4]                            ; |rs|RSDecoder:inst1|rsdec:rsdec|CSEEblock:CSEEblock|register5_wl:erroreg|dataout[4]                            ; regout           ;
; |rs|RSDecoder:inst1|rsdec:rsdec|gfadder:adder|out[0]                                                           ; |rs|RSDecoder:inst1|rsdec:rsdec|gfadder:adder|out[0]                                                           ; combout          ;
; |rs|RSDecoder:inst1|rsdec:rsdec|fifo_register:fiforeg|register5_wl:outreg|dataout[2]                           ; |rs|RSDecoder:inst1|rsdec:rsdec|fifo_register:fiforeg|register5_wl:outreg|dataout[2]                           ; regout           ;
; |rs|RSDecoder:inst1|rsdec:rsdec|CSEEblock:CSEEblock|register5_wl:erroreg|dataout[2]                            ; |rs|RSDecoder:inst1|rsdec:rsdec|CSEEblock:CSEEblock|register5_wl:erroreg|dataout[2]                            ; regout           ;
; |rs|RSDecoder:inst1|rsdec:rsdec|gfadder:adder|out[2]                                                           ; |rs|RSDecoder:inst1|rsdec:rsdec|gfadder:adder|out[2]                                                           ; combout          ;
; |rs|Clock:inst3|divide3:divideb|counter[1]                                                                     ; |rs|Clock:inst3|divide3:divideb|counter[1]                                                                     ; regout           ;
; |rs|Clock:inst3|divide3:divideb|counter[0]                                                                     ; |rs|Clock:inst3|divide3:divideb|counter[0]                                                                     ; regout           ;
; |rs|RSDecoder:inst1|fifo_decode:fifo_decode|wordstart                                                          ; |rs|RSDecoder:inst1|fifo_decode:fifo_decode|wordstart                                                          ; regout           ;
; |rs|RSDecoder:inst1|rsdec:rsdec|MainControl:controller|state1.st1_2                                            ; |rs|RSDecoder:inst1|rsdec:rsdec|MainControl:controller|state1.st1_2                                            ; regout           ;
; |rs|RSDecoder:inst1|rsdec:rsdec|MainControl:controller|state2.st2_2                                            ; |rs|RSDecoder:inst1|rsdec:rsdec|MainControl:controller|state2.st2_2                                            ; regout           ;
; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|state.st1                                                      ; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|state.st1                                                      ; regout           ;
; |rs|RSDecoder:inst1|lpm_ram_dp0:ram1|altsyncram:altsyncram_component|altsyncram_lva1:auto_generated|q_b[3]     ; |rs|RSDecoder:inst1|lpm_ram_dp0:ram1|altsyncram:altsyncram_component|altsyncram_lva1:auto_generated|q_b[3]     ; portbdataout0    ;
; |rs|RSDecoder:inst1|lpm_ram_dp0:ram1|altsyncram:altsyncram_component|altsyncram_lva1:auto_generated|q_b[3]     ; |rs|RSDecoder:inst1|lpm_ram_dp0:ram1|altsyncram:altsyncram_component|altsyncram_lva1:auto_generated|q_b[2]     ; portbdataout1    ;
; |rs|RSDecoder:inst1|lpm_ram_dp0:ram1|altsyncram:altsyncram_component|altsyncram_lva1:auto_generated|q_b[3]     ; |rs|RSDecoder:inst1|lpm_ram_dp0:ram1|altsyncram:altsyncram_component|altsyncram_lva1:auto_generated|q_b[1]     ; portbdataout2    ;
; |rs|RSDecoder:inst1|lpm_ram_dp0:ram1|altsyncram:altsyncram_component|altsyncram_lva1:auto_generated|q_b[3]     ; |rs|RSDecoder:inst1|lpm_ram_dp0:ram1|altsyncram:altsyncram_component|altsyncram_lva1:auto_generated|q_b[0]     ; portbdataout3    ;
; |rs|RSDecoder:inst1|lpm_ram_dp0:ram1|altsyncram:altsyncram_component|altsyncram_lva1:auto_generated|q_b[3]     ; |rs|RSDecoder:inst1|lpm_ram_dp0:ram1|altsyncram:altsyncram_component|altsyncram_lva1:auto_generated|q_b[4]     ; portbdataout4    ;
; |rs|RSDecoder:inst1|rsdec:rsdec|MainControl:controller|state2.st2_4                                            ; |rs|RSDecoder:inst1|rsdec:rsdec|MainControl:controller|state2.st2_4                                            ; regout           ;
; |rs|RSDecoder:inst1|rsdec:rsdec|MainControl:controller|state2.st2_3                                            ; |rs|RSDecoder:inst1|rsdec:rsdec|MainControl:controller|state2.st2_3                                            ; regout           ;
; |rs|RSDecoder:inst1|rsdec:rsdec|MainControl:controller|reduce_or~20                                            ; |rs|RSDecoder:inst1|rsdec:rsdec|MainControl:controller|reduce_or~20                                            ; combout          ;
; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_0:cell_0|gfadder:adder|out[2]~27                      ; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_0:cell_0|gfadder:adder|out[2]~27                      ; combout          ;
; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_0:cell_0|gfadder:adder|out[2]                         ; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_0:cell_0|register5_wlh:register5bit|out[2]            ; regout           ;
; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_1:cell_1|gfadder:adder|out[3]~40                      ; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_1:cell_1|gfadder:adder|out[3]~40                      ; combout          ;
; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_1:cell_1|gfadder:adder|out[2]                         ; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_1:cell_1|register5_wlh:register5bit|out[2]            ; regout           ;
; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_1:cell_1|gfadder:adder|out[3]                         ; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_1:cell_1|register5_wlh:register5bit|out[1]            ; regout           ;
; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_2:cell_2|gfadder:adder|out[4]~40                      ; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_2:cell_2|gfadder:adder|out[4]~40                      ; combout          ;
; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_2:cell_2|gfadder:adder|out[3]                         ; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_2:cell_2|register5_wlh:register5bit|out[1]            ; regout           ;
; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_2:cell_2|gfadder:adder|out[4]                         ; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_2:cell_2|register5_wlh:register5bit|out[0]            ; regout           ;
; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_3:cell_3|gfadder:adder|out[0]~45                      ; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_3:cell_3|gfadder:adder|out[0]~45                      ; combout          ;
; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_3:cell_3|gfadder:adder|out[2]                         ; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_3:cell_3|register5_wlh:register5bit|out[2]            ; regout           ;
; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_3:cell_3|gfadder:adder|out[4]                         ; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_3:cell_3|register5_wlh:register5bit|out[0]            ; regout           ;
; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_3:cell_3|gfadder:adder|out[0]                         ; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_3:cell_3|register5_wlh:register5bit|out[4]            ; regout           ;
; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_4:cell_4|gfadder:adder|out[3]~45                      ; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_4:cell_4|gfadder:adder|out[3]~45                      ; combout          ;
; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_4:cell_4|gfadder:adder|out[1]                         ; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_4:cell_4|register5_wlh:register5bit|out[3]            ; regout           ;
; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_4:cell_4|gfadder:adder|out[3]                         ; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_4:cell_4|register5_wlh:register5bit|out[1]            ; regout           ;
; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_4:cell_4|gfadder:adder|out[0]                         ; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_4:cell_4|register5_wlh:register5bit|out[4]            ; regout           ;
; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_5:cell_5|gfadder:adder|out[4]~45                      ; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_5:cell_5|gfadder:adder|out[4]~45                      ; combout          ;
; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_5:cell_5|gfadder:adder|out[1]                         ; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_5:cell_5|register5_wlh:register5bit|out[3]            ; regout           ;
; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_5:cell_5|gfadder:adder|out[4]                         ; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_5:cell_5|register5_wlh:register5bit|out[0]            ; regout           ;
; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_6:cell_6|gfadder:adder|out[0]~27                      ; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_6:cell_6|gfadder:adder|out[0]~27                      ; combout          ;
; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_6:cell_6|gfadder:adder|out[0]                         ; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_6:cell_6|register5_wlh:register5bit|out[4]            ; regout           ;
; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_7:cell_7|gfadder:adder|out[1]~27                      ; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_7:cell_7|gfadder:adder|out[1]~27                      ; combout          ;
; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_7:cell_7|gfadder:adder|out[1]                         ; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_7:cell_7|register5_wlh:register5bit|out[3]            ; regout           ;
; |rs|RSDecoder:inst1|divide5:dividec|counter[0]                                                                 ; |rs|RSDecoder:inst1|divide5:dividec|counter[0]                                                                 ; regout           ;
; |rs|RSDecoder:inst1|divide5:dividec|counter[2]                                                                 ; |rs|RSDecoder:inst1|divide5:dividec|counter[2]                                                                 ; regout           ;
; |rs|RSDecoder:inst1|divide5:dividec|counter[1]                                                                 ; |rs|RSDecoder:inst1|divide5:dividec|counter[1]                                                                 ; regout           ;
; |rs|RSDecoder:inst1|rsdec:rsdec|MainControl:controller|cntdatain[2]