top.sim.rpt

RS编码的verilog源代码

; |rs|RSDecoder:inst1|lpm_ram_dp0:ram2|altsyncram:altsyncram_component|altsyncram_lva1:auto_generated|q_b[3]     ; |rs|RSDecoder:inst1|lpm_ram_dp0:ram2|altsyncram:altsyncram_component|altsyncram_lva1:auto_generated|q_b[2]     ; portbdataout2    ;
; |rs|RSDecoder:inst1|lpm_ram_dp0:ram2|altsyncram:altsyncram_component|altsyncram_lva1:auto_generated|q_b[3]     ; |rs|RSDecoder:inst1|lpm_ram_dp0:ram2|altsyncram:altsyncram_component|altsyncram_lva1:auto_generated|q_b[0]     ; portbdataout3    ;
; |rs|RSDecoder:inst1|lpm_ram_dp0:ram2|altsyncram:altsyncram_component|altsyncram_lva1:auto_generated|q_b[3]     ; |rs|RSDecoder:inst1|lpm_ram_dp0:ram2|altsyncram:altsyncram_component|altsyncram_lva1:auto_generated|q_b[1]     ; portbdataout4    ;
; |rs|RSDecoder:inst1|Dec2Bit:Dec2Bit|cnt[2]                                                                     ; |rs|RSDecoder:inst1|Dec2Bit:Dec2Bit|cnt[2]                                                                     ; regout           ;
; |rs|RSDecoder:inst1|Dec2Bit:Dec2Bit|Equal~149                                                                  ; |rs|RSDecoder:inst1|Dec2Bit:Dec2Bit|Equal~149                                                                  ; combout          ;
; |rs|RSDecoder:inst1|Dec2Bit:Dec2Bit|buff~1117                                                                  ; |rs|RSDecoder:inst1|Dec2Bit:Dec2Bit|buff~1117                                                                  ; combout          ;
; |rs|RSDecoder:inst1|Dec2Bit:Dec2Bit|buff~1118                                                                  ; |rs|RSDecoder:inst1|Dec2Bit:Dec2Bit|buff~1118                                                                  ; combout          ;
; |rs|RSDecoder:inst1|Dec2Bit:Dec2Bit|Select~319                                                                 ; |rs|RSDecoder:inst1|Dec2Bit:Dec2Bit|Select~319                                                                 ; combout          ;
; |rs|RSDecoder:inst1|Dec2Bit:Dec2Bit|buff~1119                                                                  ; |rs|RSDecoder:inst1|Dec2Bit:Dec2Bit|buff~1119                                                                  ; combout          ;
; |rs|RSDecoder:inst1|Dec2Bit:Dec2Bit|Select~320                                                                 ; |rs|RSDecoder:inst1|Dec2Bit:Dec2Bit|Select~320                                                                 ; combout          ;
; |rs|Clock:inst3|divide3:divideb|clk_out                                                                        ; |rs|Clock:inst3|divide3:divideb|clk_out                                                                        ; combout          ;
; |rs|RSDecoder:inst1|rsdec:rsdec|MainControl:controller|state1.st1_3                                            ; |rs|RSDecoder:inst1|rsdec:rsdec|MainControl:controller|state1.st1_3                                            ; regout           ;
; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|state.st2                                                      ; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|state.st2                                                      ; regout           ;
; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_0:cell_0|register5_wlh:register5bit|out[3]            ; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_0:cell_0|register5_wlh:register5bit|out[3]            ; regout           ;
; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_0:cell_0|register5_wlh:register5bit|out[1]            ; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_0:cell_0|register5_wlh:register5bit|out[1]            ; regout           ;
; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_0:cell_0|register5_wlh:register5bit|out[0]            ; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_0:cell_0|register5_wlh:register5bit|out[0]            ; regout           ;
; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|always2~773                                                    ; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|always2~773                                                    ; combout          ;
; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_0:cell_0|register5_wlh:register5bit|out[4]            ; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_0:cell_0|register5_wlh:register5bit|out[4]            ; regout           ;
; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_1:cell_1|register5_wlh:register5bit|out[3]            ; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_1:cell_1|register5_wlh:register5bit|out[3]            ; regout           ;
; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|always2~774                                                    ; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|always2~774                                                    ; combout          ;
; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_1:cell_1|register5_wlh:register5bit|out[0]            ; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_1:cell_1|register5_wlh:register5bit|out[0]            ; regout           ;
; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_1:cell_1|register5_wlh:register5bit|out[4]            ; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_1:cell_1|register5_wlh:register5bit|out[4]            ; regout           ;
; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_2:cell_2|register5_wlh:register5bit|out[3]            ; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_2:cell_2|register5_wlh:register5bit|out[3]            ; regout           ;
; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_2:cell_2|register5_wlh:register5bit|out[2]            ; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_2:cell_2|register5_wlh:register5bit|out[2]            ; regout           ;
; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|always2~775                                                    ; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|always2~775                                                    ; combout          ;
; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_2:cell_2|register5_wlh:register5bit|out[4]            ; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_2:cell_2|register5_wlh:register5bit|out[4]            ; regout           ;
; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|always2~776                                                    ; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|always2~776                                                    ; combout          ;
; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|always2~777                                                    ; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|always2~777                                                    ; combout          ;
; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|always2~778                                                    ; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|always2~778                                                    ; combout          ;
; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_4:cell_4|register5_wlh:register5bit|out[2]            ; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_4:cell_4|register5_wlh:register5bit|out[2]            ; regout           ;
; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_4:cell_4|register5_wlh:register5bit|out[0]            ; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_4:cell_4|register5_wlh:register5bit|out[0]            ; regout           ;
; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|always2~779                                                    ; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|always2~779                                                    ; combout          ;
; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|always2~780                                                    ; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|always2~780                                                    ; combout          ;
; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_5:cell_5|register5_wlh:register5bit|out[4]            ; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_5:cell_5|register5_wlh:register5bit|out[4]            ; regout           ;
; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_6:cell_6|register5_wlh:register5bit|out[2]            ; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_6:cell_6|register5_wlh:register5bit|out[2]            ; regout           ;
; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|always2~781                                                    ; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|always2~781                                                    ; combout          ;
; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|always2~782                                                    ; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|always2~782                                                    ; combout          ;
; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_6:cell_6|register5_wlh:register5bit|out[1]            ; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_6:cell_6|register5_wlh:register5bit|out[1]            ; regout           ;
; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_6:cell_6|register5_wlh:register5bit|out[0]            ; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_6:cell_6|register5_wlh:register5bit|out[0]            ; regout           ;
; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|always2~783                                                    ; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|always2~783                                                    ; combout          ;
; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_7:cell_7|register5_wlh:register5bit|out[4]            ; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_7:cell_7|register5_wlh:register5bit|out[4]            ; regout           ;
; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|always2~784                                                    ; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|always2~784                                                    ; combout          ;
; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_8:cell_8|register5_wlh:register5bit|out[2]            ; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_8:cell_8|register5_wlh:register5bit|out[2]            ; regout           ;
; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_8:cell_8|register5_wlh:register5bit|out[1]            ; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_8:cell_8|register5_wlh:register5bit|out[1]            ; regout           ;
; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_8:cell_8|register5_wlh:register5bit|out[0]            ; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_8:cell_8|register5_wlh:register5bit|out[0]            ; regout           ;
; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|always2~785                                                    ; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|always2~785                                                    ; combout          ;
; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_8:cell_8|register5_wlh:register5bit|out[4]            ; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_8:cell_8|register5_wlh:register5bit|out[4]            ; regout           ;
; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_9:cell_9|register5_wlh:register5bit|out[3]            ; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_9:cell_9|register5_wlh:register5bit|out[3]            ; regout           ;
; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_9:cell_9|register5_wlh:register5bit|out[2]            ; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_9:cell_9|register5_wlh:register5bit|out[2]            ; regout           ;
; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_9:cell_9|register5_wlh:register5bit|out[1]            ; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_9:cell_9|register5_wlh:register5bit|out[1]            ; regout           ;
; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|always2~786                                                    ; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|always2~786                                                    ; combout          ;
; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|always2~787                                                    ; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|always2~787                                                    ; combout          ;
; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_9:cell_9|register5_wlh:register5bit|out[0]            ; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_9:cell_9|register5_wlh:register5bit|out[0]            ; regout           ;
; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_9:cell_9|register5_wlh:register5bit|out[4]            ; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_9:cell_9|register5_wlh:register5bit|out[4]            ; regout           ;
; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_10:cell_10|register5_wlh:register5bit|out[2]          ; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_10:cell_10|register5_wlh:register5bit|out[2]          ; regout           ;
; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|always2~788                                                    ; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|always2~788                                                    ; combout          ;
; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_10:cell_10|register5_wlh:register5bit|out[1]          ; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_10:cell_10|register5_wlh:register5bit|out[1]          ; regout           ;
; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_10:cell_10|register5_wlh:register5bit|out[0]          ; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_10:cell_10|register5_wlh:register5bit|out[0]          ; regout           ;
; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_10:cell_10|register5_wlh:register5bit|out[4]          ; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_10:cell_10|register5_wlh:register5bit|out[4]          ; regout           ;
; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_11:cell_11|register5_wlh:register5bit|out[3]          ; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_11:cell_11|register5_wlh:register5bit|out[3]          ; regout           ;
; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|always2~789                                                    ; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|always2~789                                                    ; combout          ;
; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_11:cell_11|register5_wlh:register5bit|out[2]          ; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_11:cell_11|register5_wlh:register5bit|out[2]          ; regout           ;
; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_11:cell_11|register5_wlh:register5bit|out[1]          ; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_11:cell_11|register5_wlh:register5bit|out[1]          ; regout           ;
; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_11:cell_11|register5_wlh:register5bit|out[0]          ; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_11:cell_11|register5_wlh:register5bit|out[0]          ; regout           ;
; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_11:cell_11|register5_wlh:register5bit|out[4]          ; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_11:cell_11|register5_wlh:register5bit|out[4]          ; regout           ;
; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|always2~790                                                    ; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|always2~790                                                    ; combout          ;
; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|always2~791                                                    ; |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|always2~791                                                    ; combout          ;
; |rs|RSDecoder:inst1|rsdec:rsdec|MainControl:controller|nxt_state1.st1_4~10                                     ; |rs|RSDecoder:inst1|rsdec:rsdec|MainControl:controller|nxt_state1.st1_4~10                                     ; combout          ;
; |rs|RSDecoder:inst1|divide5:dividec|clk_out                                                                    ; |rs|RSDecoder:inst1|divide5:dividec|clk_out                                                                    ; combout          ;
; |rs|RSDecoder:inst1|rsdec:rsdec|MainControl:controller|state2.st2_11                                           ; |rs|RSDecoder:inst1|rsdec:rsdec|MainControl:controller|state2.st2_11                                           ; regout           ;
; |rs|RSDecoder:inst1|rsdec:rsdec|MainControl:controller|reduce_or~82                                            ; |rs|RSDecoder:inst1|rsdec:rsdec|MainControl:controller|reduce_or~82                                            ; combout          ;
; |rs|RSDecoder:inst1|rsdec:rsdec|MainControl:controller|state1.st1_9                                            ; |rs|RSDecoder:inst1|rsdec:rsdec|MainControl:controller|state1.st1_9                                            ; regout           ;