top.sim.rpt

RS编码的verilog源代码

; Disable timing delays in Timing Simulation                      ; Off                                                    ; Off           ;
; Generate Signal Activity File                                   ; Off                                                    ; Off           ;
; Group bus channels in simulation results                        ; Off                                                    ; Off           ;
; Preserve fewer signal transitions to reduce memory requirements ; On                                                     ; On            ;
; Overwrite Waveform Inputs With Simulation Outputs               ; Off                                                    ;               ;
+-----------------------------------------------------------------+--------------------------------------------------------+---------------+


+----------------------+
; Simulation Waveforms ;
+----------------------+
Waveform report data cannot be output to ASCII.
Please use Quartus II to view the waveform report data.


+----------------------------------------------------------------------------------------------------------------+
; |rs|RSDecoder:inst1|lpm_ram_dp0:ram2|altsyncram:altsyncram_component|altsyncram_lva1:auto_generated|ALTSYNCRAM ;
+----------------------------------------------------------------------------------------------------------------+
Memory report data cannot be output to ASCII.
Please use Quartus II to view the memory report data.


+------------------------------------------------------------------------------------------------------------+
; |rs|RSEncoder:inst|lpm_ram_dp0:C|altsyncram:altsyncram_component|altsyncram_lva1:auto_generated|ALTSYNCRAM ;
+------------------------------------------------------------------------------------------------------------+
Memory report data cannot be output to ASCII.
Please use Quartus II to view the memory report data.


+----------------------------------------------------------------------------------------------------------------+
; |rs|RSDecoder:inst1|lpm_ram_dp0:ram1|altsyncram:altsyncram_component|altsyncram_lva1:auto_generated|ALTSYNCRAM ;
+----------------------------------------------------------------------------------------------------------------+
Memory report data cannot be output to ASCII.
Please use Quartus II to view the memory report data.


+--------------------------------------------------------------------+
; Coverage Summary                                                   ;
+-----------------------------------------------------+--------------+
; Type                                                ; Value        ;
+-----------------------------------------------------+--------------+
; Total coverage as a percentage                      ;      94.06 % ;
; Total nodes checked                                 ; 1624         ;
; Total output ports checked                          ; 1651         ;
; Total output ports with complete 1/0-value coverage ; 1553         ;
; Total output ports with no 1/0-value coverage       ; 72           ;
; Total output ports with no 1-value coverage         ; 72           ;
; Total output ports with no 0-value coverage         ; 98           ;
+-----------------------------------------------------+--------------+


The following table displays output ports that toggle between 1 and 0 during simulation.
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Complete 1/0-Value Coverage                                                                                                                                                                                                                        ;
+----------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------+------------------+
; Node Name                                                                                                      ; Output Port Name                                                                                               ; Output Port Type ;
+----------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------+------------------+
; |rs|RSDecoder:inst1|Dec2Bit:Dec2Bit|out                                                                        ; |rs|RSDecoder:inst1|Dec2Bit:Dec2Bit|out                                                                        ; regout           ;
; |rs|RSDecoder:inst1|Dec2Bit:Dec2Bit|outstart                                                                   ; |rs|RSDecoder:inst1|Dec2Bit:Dec2Bit|outstart                                                                   ; regout           ;
; |rs|RSDecoder:inst1|rsdec:rsdec|MainControl:controller|state1.st1_4                                            ; |rs|RSDecoder:inst1|rsdec:rsdec|MainControl:controller|state1.st1_4                                            ; regout           ;
; |rs|RSDecoder:inst1|rsdec:rsdec|MainControl:controller|state1.st1_11                                           ; |rs|RSDecoder:inst1|rsdec:rsdec|MainControl:controller|state1.st1_11                                           ; regout           ;
; |rs|RSDecoder:inst1|rsdec:rsdec|MainControl:controller|decode_fail                                             ; |rs|RSDecoder:inst1|rsdec:rsdec|MainControl:controller|decode_fail                                             ; combout          ;
; |rs|nrz:inst2|out                                                                                              ; |rs|nrz:inst2|out                                                                                              ; regout           ;
; |rs|error:inst6|errorout                                                                                       ; |rs|error:inst6|errorout                                                                                       ; regout           ;
; |rs|inst17                                                                                                     ; |rs|inst17                                                                                                     ; regout           ;
; |rs|RSEncoder:inst|Dec2Bit:E|out                                                                               ; |rs|RSEncoder:inst|Dec2Bit:E|out                                                                               ; regout           ;
; |rs|RSDecoder:inst1|Dec2Bit:Dec2Bit|cnt[0]                                                                     ; |rs|RSDecoder:inst1|Dec2Bit:Dec2Bit|cnt[0]                                                                     ; regout           ;
; |rs|RSDecoder:inst1|Dec2Bit:Dec2Bit|Select~317                                                                 ; |rs|RSDecoder:inst1|Dec2Bit:Dec2Bit|Select~317                                                                 ; combout          ;
; |rs|RSDecoder:inst1|Dec2Bit:Dec2Bit|cnt[1]                                                                     ; |rs|RSDecoder:inst1|Dec2Bit:Dec2Bit|cnt[1]                                                                     ; regout           ;
; |rs|RSDecoder:inst1|Dec2Bit:Dec2Bit|Select~318                                                                 ; |rs|RSDecoder:inst1|Dec2Bit:Dec2Bit|Select~318                                                                 ; combout          ;
; |rs|RSDecoder:inst1|lpm_ram_dp0:ram2|altsyncram:altsyncram_component|altsyncram_lva1:auto_generated|q_b[3]     ; |rs|RSDecoder:inst1|lpm_ram_dp0:ram2|altsyncram:altsyncram_component|altsyncram_lva1:auto_generated|q_b[3]     ; portbdataout0    ;
; |rs|RSDecoder:inst1|lpm_ram_dp0:ram2|altsyncram:altsyncram_component|altsyncram_lva1:auto_generated|q_b[3]     ; |rs|RSDecoder:inst1|lpm_ram_dp0:ram2|altsyncram:altsyncram_component|altsyncram_lva1:auto_generated|q_b[4]     ; portbdataout1    ;