top.map.smsg

RS编码的verilog源代码

Info: Elaborating entity "syndcell_6" for hierarchy "RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_6:cell_6"
Info: Elaborating entity "syndcell_7" for hierarchy "RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_7:cell_7"
Info: Elaborating entity "syndcell_8" for hierarchy "RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_8:cell_8"
Info: Elaborating entity "syndcell_9" for hierarchy "RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_9:cell_9"
Info: Elaborating entity "syndcell_10" for hierarchy "RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_10:cell_10"
Info: Elaborating entity "syndcell_11" for hierarchy "RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_11:cell_11"
Info: Elaborating entity "KES_block" for hierarchy "RSDecoder:inst1|rsdec:rsdec|KES_block:KESblock"
Info: Elaborating entity "PE" for hierarchy "RSDecoder:inst1|rsdec:rsdec|KES_block:KESblock|PE:PE0"
Info: Elaborating entity "lcpmult" for hierarchy "RSDecoder:inst1|rsdec:rsdec|KES_block:KESblock|PE:PE0|lcpmult:multiplier1"
Info: Elaborating entity "register_pe" for hierarchy "RSDecoder:inst1|rsdec:rsdec|KES_block:KESblock|PE:PE0|register_pe:reg1"
Info: Elaborating entity "mux2_to_1" for hierarchy "RSDecoder:inst1|rsdec:rsdec|KES_block:KESblock|PE:PE0|mux2_to_1:multiplexer"
Info: Elaborating entity "PE_12" for hierarchy "RSDecoder:inst1|rsdec:rsdec|KES_block:KESblock|PE_12:PE12"
Info: Elaborating entity "PE_18" for hierarchy "RSDecoder:inst1|rsdec:rsdec|KES_block:KESblock|PE_18:PE18"
Info: Elaborating entity "control" for hierarchy "RSDecoder:inst1|rsdec:rsdec|KES_block:KESblock|control:mcontrol"
Warning (10230): Verilog HDL assignment warning at KESBLOCK.V(129): truncated value with size 32 to match size of target (4)
Info: Elaborating entity "fulladder" for hierarchy "RSDecoder:inst1|rsdec:rsdec|KES_block:KESblock|control:mcontrol|fulladder:adder"
Info: Elaborating entity "regamma" for hierarchy "RSDecoder:inst1|rsdec:rsdec|KES_block:KESblock|control:mcontrol|regamma:reggamma"
Info: Elaborating entity "regkr" for hierarchy "RSDecoder:inst1|rsdec:rsdec|KES_block:KESblock|control:mcontrol|regkr:regkr"
Info: Elaborating entity "priority_encoder" for hierarchy "RSDecoder:inst1|rsdec:rsdec|KES_block:KESblock|priority_encoder:pencoder"
Info: Elaborating entity "CSEEblock" for hierarchy "RSDecoder:inst1|rsdec:rsdec|CSEEblock:CSEEblock"
Warning (10230): Verilog HDL assignment warning at CSEEBLOCK.v(38): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at CSEEBLOCK.v(48): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at CSEEBLOCK.v(50): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at CSEEBLOCK.v(54): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at CSEEBLOCK.v(56): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at CSEEBLOCK.v(58): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at CSEEBLOCK.v(89): truncated value with size 32 to match size of target (3)
Info: Elaborating entity "degree0_cell" for hierarchy "RSDecoder:inst1|rsdec:rsdec|CSEEblock:CSEEblock|degree0_cell:cs0_cell"
Info: Elaborating entity "register5_wl" for hierarchy "RSDecoder:inst1|rsdec:rsdec|CSEEblock:CSEEblock|degree0_cell:cs0_cell|register5_wl:register"
Info: Elaborating entity "degree1_cell" for hierarchy "RSDecoder:inst1|rsdec:rsdec|CSEEblock:CSEEblock|degree1_cell:cs1_cell"
Info: Elaborating entity "degree2_cell" for hierarchy "RSDecoder:inst1|rsdec:rsdec|CSEEblock:CSEEblock|degree2_cell:cs2_cell"
Info: Elaborating entity "degree3_cell" for hierarchy "RSDecoder:inst1|rsdec:rsdec|CSEEblock:CSEEblock|degree3_cell:cs3_cell"
Info: Elaborating entity "degree4_cell" for hierarchy "RSDecoder:inst1|rsdec:rsdec|CSEEblock:CSEEblock|degree4_cell:cs4_cell"
Info: Elaborating entity "degree5_cell" for hierarchy "RSDecoder:inst1|rsdec:rsdec|CSEEblock:CSEEblock|degree5_cell:cs5_cell"
Info: Elaborating entity "degree6_cell" for hierarchy "RSDecoder:inst1|rsdec:rsdec|CSEEblock:CSEEblock|degree6_cell:cs6_cell"
Info: Elaborating entity "inverscomb" for hierarchy "RSDecoder:inst1|rsdec:rsdec|CSEEblock:CSEEblock|inverscomb:invers"
Info: Elaborating entity "MainControl" for hierarchy "RSDecoder:inst1|rsdec:rsdec|MainControl:controller"
Warning (10230): Verilog HDL assignment warning at DEcontroller.v(552): truncated value with size 32 to match size of target (5)
Warning (10230): Verilog HDL assignment warning at DEcontroller.v(560): truncated value with size 32 to match size of target (5)
Info: Elaborating entity "fifo_register" for hierarchy "RSDecoder:inst1|rsdec:rsdec|fifo_register:fiforeg"
Info: Elaborating entity "fifo_decode" for hierarchy "RSDecoder:inst1|fifo_decode:fifo_decode"
Warning (10230): Verilog HDL assignment warning at RAM_fifo_all.v(133): truncated value with size 32 to match size of target (6)
Warning (10230): Verilog HDL assignment warning at RAM_fifo_all.v(141): truncated value with size 32 to match size of target (6)
Warning (10230): Verilog HDL assignment warning at RAM_fifo_all.v(142): truncated value with size 6 to match size of target (5)
Warning (10240): Verilog HDL Always Construct warning at RAM_fifo_all.v(103): inferring latch(es) for variable "isword1", which holds its previous value in one or more paths through the always construct
Info (10041): Verilog HDL or VHDL info at RAM_fifo_all.v(98): inferred latch for "isword1"
Warning (10230): Verilog HDL assignment warning at RAM_fifo_all.v(178): truncated value with size 32 to match size of target (5)
Info: Elaborating entity "Dec2Bit" for hierarchy "RSDecoder:inst1|Dec2Bit:Dec2Bit"
Warning (10230): Verilog HDL assignment warning at serial_paralled_conversion.v(35): truncated value with size 32 to match size of target (3)
Info: Elaborating entity "Clock" for hierarchy "Clock:inst3"
Info: Elaborating entity "pll" for hierarchy "Clock:inst3|pll:p31_57"
Info: Found 1 design units, including 1 entities, in source file f:/altera/70/quartus/libraries/megafunctions/altpll.tdf
    Info: Found entity 1: altpll
Info: Elaborating entity "altpll" for hierarchy "Clock:inst3|pll:p31_57|altpll:altpll_component"
Info: Elaborated megafunction instantiation "Clock:inst3|pll:p31_57|altpll:altpll_component"
Info: Elaborating entity "divide3" for hierarchy "Clock:inst3|divide3:divideb"
Warning (10230): Verilog HDL assignment warning at frequency divider.v(57): truncated value with size 32 to match size of target (3)
Info: Elaborating entity "RSEncoder" for hierarchy "RSEncoder:inst"
Info: Elaborating entity "fifo_encode" for hierarchy "RSEncoder:inst|fifo_encode:B"
Warning (10230): Verilog HDL assignment warning at RAM_fifo_all.v(41): truncated value with size 32 to match size of target (5)
Warning (10230): Verilog HDL assignment warning at RAM_fifo_all.v(43): truncated value with size 32 to match size of target (5)
Warning (10230): Verilog HDL assignment warning at RAM_fifo_all.v(70): truncated value with size 32 to match size of target (6)
Warning (10230): Verilog HDL assignment warning at RAM_fifo_all.v(71): truncated value with size 6 to match size of target (5)
Info: Elaborating entity "rsenc" for hierarchy "RSEncoder:inst|rsenc:D"
Info: Elaborating entity "mul" for hierarchy "RSEncoder:inst|rsenc:D|mul:m0"
Info: Elaborating entity "nrz" for hierarchy "nrz:inst2"
Warning (10230): Verilog HDL assignment warning at source_nrz.v(20): truncated value with size 32 to match size of target (3)
Warning: Port "ordered port 0" on the entity instantiation of "m11" is connected to a signal of width 32. The formal width of the signal in the module is 5.  Extra bits will be ignored.
Warning: Port "ordered port 0" on the entity instantiation of "m10" is connected to a signal of width 32. The formal width of the signal in the module is 5.  Extra bits will be ignored.
Warning: Port "ordered port 0" on the entity instantiation of "m9" is connected to a signal of width 32. The formal width of the signal in the module is 5.  Extra bits will be ignored.
Warning: Port "ordered port 0" on the entity instantiation of "m8" is connected to a signal of width 32. The formal width of the signal in the module is 5.  Extra bits will be ignored.
Warning: Port "ordered port 0" on the entity instantiation of "m7" is connected to a signal of width 32. The formal width of the signal in the module is 5.  Extra bits will be ignored.
Warning: Port "ordered port 0" on the entity instantiation of "m6" is connected to a signal of width 32. The formal width of the signal in the module is 5.  Extra bits will be ignored.
Warning: Port "ordered port 0" on the entity instantiation of "m5" is connected to a signal of width 32. The formal width of the signal in the module is 5.  Extra bits will be ignored.
Warning: Port "ordered port 0" on the entity instantiation of "m4" is connected to a signal of width 32. The formal width of the signal in the module is 5.  Extra bits will be ignored.
Warning: Port "ordered port 0" on the entity instantiation of "m3" is connected to a signal of width 32. The formal width of the signal in the module is 5.  Extra bits will be ignored.
Warning: Port "ordered port 0" on the entity instantiation of "m2" is connected to a signal of width 32. The formal width of the signal in the module is 5.  Extra bits will be ignored.
Warning: Port "ordered port 0" on the entity instantiation of "m1" is connected to a signal of width 32. The formal width of the signal in the module is 5.  Extra bits will be ignored.
Warning: Port "ordered port 0" on the entity instantiation of "m0" is connected to a signal of width 32. The formal width of the signal in the module is 5.  Extra bits will be ignored.
Warning: Port "ordered port 1" on the entity instantiation of "divideb" is connected to a signal of width 32. The formal width of the signal in the module is 1.  Extra bits will be ignored.
Warning: Port "ordered port 1" on the entity instantiation of "dividea" is connected to a signal of width 32. The formal width of the signal in the module is 1.  Extra bits will be ignored.
Warning: Port "ordered port 1" on the entity instantiation of "divideb" is connected to a signal of width 32. The formal width of the signal in the module is 1.  Extra bits will be ignored.
Warning: Port "ordered port 0" on the entity instantiation of "p31_57" is connected to a signal of width 32. The formal width of the signal in the module is 1.  Extra bits will be ignored.
Warning: Port "ordered port 1" on the entity instantiation of "dividec" is connected to a signal of width 32. The formal width of the signal in the module is 1.  Extra bits will be ignored.
Warning: Port "ordered port 1" on the entity instantiation of "divideb" is connected to a signal of width 32. The formal width of the signal in the module is 1.  Extra bits will be ignored.
Warning: Port "ordered port 1" on the entity instantiation of "dividea" is connected to a signal of width 32. The formal width of the signal in the module is 1.  Extra bits will be ignored.
Info: Duplicate registers merged to single register
    Info: Duplicate register "RSDecoder:inst1|before_decode:before_decode|wren" merged to single register "RSDecoder:inst1|before_decode:before_decode|wrclocken"
    Info: Duplicate register "RSEncoder:inst|fifo_encode:B|wren" merged to single register "RSEncoder:inst|fifo_encode:B|wrclocken"
    Info: Duplicate register "RSEncoder:inst|fifo_encode:B|temp1[4]" merged to single register "RSEncoder:inst|fifo_encode:B|rdaddress[4]"
    Info: Duplicate register "RSEncoder:inst|fifo_encode:B|temp1[3]" merged to single register "RSEncoder:inst|fifo_encode:B|rdaddress[3]"
    Info: Duplicate register "RSEncoder:inst|fifo_encode:B|temp1[2]" merged to single register "RSEncoder:inst|fifo_encode:B|rdaddress[2]"
    Info: Duplicate register "RSEncoder:inst|fifo_encode:B|temp1[1]" merged to single register "RSEncoder:inst|fifo_encode:B|rdaddress[1]"
    Info: Duplicate register "RSEncoder:inst|fifo_encode:B|temp1[0]" merged to single register "RSEncoder:inst|fifo_encode:B|rdaddress[0]"
    Info: Duplicate register "RSDecoder:inst1|fifo_decode:fifo_decode|temp2[4]" merged to single register "RSDecoder:inst1|fifo_decode:fifo_decode|rdaddress[4]"
    Info: Duplicate register "RSDecoder:inst1|fifo_decode:fifo_decode|temp2[3]" merged to single register "RSDecoder:inst1|fifo_decode:fifo_decode|rdaddress[3]"
    Info: Duplicate register "RSDecoder:inst1|fifo_decode:fifo_decode|temp2[2]" merged to single register "RSDecoder:inst1|fifo_decode:fifo_decode|rdaddress[2]"
    Info: Duplicate register "RSDecoder:inst1|fifo_decode:fifo_decode|temp2[1]" merged to single register "RSDecoder:inst1|fifo_decode:fifo_decode|rdaddress[1]"
    Info: Duplicate register "RSDecoder:inst1|fifo_decode:fifo_decode|temp2[0]" merged to single register "RSDecoder:inst1|fifo_decode:fifo_decode|rdaddress[0]"
    Info: Duplicate register "RSDecoder:inst1|rsdec:rsdec|KES_block:KESblock|PE_18:PE18|register_pe:reg2|out[2]" merged to single register "RSDecoder:inst1|rsdec:rsdec|KES_block:KESblock|PE_18:PE18|register_pe:reg2|out[3]"
    Info: Duplicate register "RSDecoder:inst1|rsdec:rsdec|KES_block:KESblock|PE_18:PE18|register_pe:reg2|out[1]" merged to single register "RSDecoder:inst1|rsdec:rsdec|KES_block:KESblock|PE_18:PE18|register_pe:reg2|out[3]"
    Info: Duplicate register "RSDecoder:inst1|rsdec:rsdec|KES_block:KESblock|PE_18:PE18|register_pe:reg2|out[0]" merged to single register "RSDecoder:inst1|rsdec:rsdec|KES_block:KESblock|PE_18:PE18|register_pe:reg2|out[3]"
Info: Duplicate registers merged to single register
    Info: Duplicate register "RSDecoder:inst1|divide5:divideb|clk_temp1" merged to single register "RSEncoder:inst|divide5:divideb|clk_temp1"
    Info: Duplicate register "RSDecoder:inst1|divide5:divideb|clk_temp2" merged to single register "RSEncoder:inst|divide5:divideb|clk_temp2"
    Info: Duplicate register "RSDecoder:inst1|divide5:dividea|clk_temp1" merged to single register "RSEncoder:inst|divide5:dividea|clk_temp1"
    Info: Duplicate register "RSDecoder:inst1|divide5:dividea|clk_temp2" merged to single register "RSEncoder:inst|divide5:dividea|clk_temp2"
Warning: Reduced register "RSDecoder:inst1|rsdec:rsdec|KES_block:KESblock|PE_18:PE18|register_pe:reg2|out[3]" with stuck data_in port to stuck value GND
Info: State machine "|rs|RSDecoder:inst1|rsdec:rsdec|MainControl:controller|state1" contains 15 states
Info: State machine "|rs|RSDecoder:inst1|rsdec:rsdec|MainControl:controller|state2" contains 12 states
Info: State machine "|rs|RSDecoder:inst1|rsdec:rsdec|KES_block:KESblock|control:mcontrol|state" contains 5 states
Info: State machine "|rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|state" contains 3 states