top.fit.smsg

RS编码的verilog源代码

Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Tue Jun 12 11:11:00 2007
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off RS_encode_and_decode -c top
Info: Selected device EP1C6Q240C8 for design "top"
Info: Implementing parameter values for PLL "Clock:inst3|pll:p31_57|altpll:altpll_component|pll"
    Info: Implementing clock multiplication of 31, clock division of 57, and phase shift of 0 degrees (0 ps) for Clock:inst3|pll:p31_57|altpll:altpll_component|_clk0 port
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EP1C12Q240C8 is compatible
Info: Fitter converted 2 user pins into dedicated programming pins
    Info: Pin ~nCSO~ is reserved at location 24
    Info: Pin ~ASDO~ is reserved at location 37
Info: Fitter is using the Classic Timing Analyzer
Info: Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements
Info: Completed User Assigned Global Signals Promotion Operation
Info: DQS I/O pins require 0 global routing resources
Info: Promoted PLL clock signals
    Info: Promoted signal "clk" to use global clock
    Info: Promoted signal "Clock:inst3|pll:p31_57|altpll:altpll_component|_clk0" to use global clock (user assigned)
Info: Completed PLL Placement Operation
Info: Automatically promoted signal "RSDecoder:inst1|divide5:dividec|clk_out" to use Global clock
Info: Automatically promoted signal "RSDecoder:inst1|divide5:divideb|clk_out" to use Global clock
Info: Automatically promoted signal "Clock:inst3|divide3:divideb|clk_out" to use Global clock
Info: Automatically promoted signal "RSDecoder:inst1|divide5:dividea|clk_out" to use Global clock
Info: Automatically promoted some destinations of signal "reset" to use Global clock
    Info: Destination "nrz:inst2|c5" may be non-global or may not use global clock
    Info: Destination "RSDecoder:inst1|Dec2Bit:Dec2Bit|buff[4]~1126" may be non-global or may not use global clock
    Info: Destination "nrz:inst2|c4" may be non-global or may not use global clock
    Info: Destination "RSDecoder:inst1|fifo_decode:fifo_decode|comb~0" may be non-global or may not use global clock
    Info: Destination "RSDecoder:inst1|fifo_decode:fifo_decode|wraddress~10" may be non-global or may not use global clock
    Info: Destination "nrz:inst2|c3" may be non-global or may not use global clock
    Info: Destination "nrz:inst2|c2" may be non-global or may not use global clock
    Info: Destination "RSDecoder:inst1|Bit2Dec:Bit2Dec|c4~12" may be non-global or may not use global clock
    Info: Destination "nrz:inst2|c1" may be non-global or may not use global clock
    Info: Destination "RSEncoder:inst|Dec2Bit:E|buff[4]~1971" may be non-global or may not use global clock
    Info: Limited to 10 non-global destinations
Info: Pin "reset" drives global clock, but is not placed in a dedicated clock pin position
Info: Automatically promoted signal "RSDecoder:inst1|fifo_decode:fifo_decode|wraddress~10" to use Global clock
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Finished moving registers into I/O cells, LUTs, and RAM blocks
Info: Finished register packing: elapsed time is 00:00:01
Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:13
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:41
Info: Estimated most critical path is register to register delay of 2.916 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X15_Y3; Fanout = 4; REG Node = 'RSEncoder:inst|fifo_encode:B|temp[2]'
    Info: 2: + IC(0.615 ns) + CELL(0.114 ns) = 0.729 ns; Loc. = LAB_X15_Y3; Fanout = 1; COMB Node = 'RSEncoder:inst|fifo_encode:B|always2~296'
    Info: 3: + IC(0.211 ns) + CELL(0.442 ns) = 1.382 ns; Loc. = LAB_X15_Y3; Fanout = 8; COMB Node = 'RSEncoder:inst|fifo_encode:B|always2~0'
    Info: 4: + IC(0.667 ns) + CELL(0.867 ns) = 2.916 ns; Loc. = LAB_X14_Y3; Fanout = 1; REG Node = 'RSEncoder:inst|fifo_encode:B|wordstart'
    Info: Total cell delay = 1.423 ns ( 48.80 % )
    Info: Total interconnect delay = 1.493 ns ( 51.20 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 6% of the available device resources. Peak interconnect usage is 13%
    Info: The peak interconnect region extends from location X12_Y0 to location X23_Y10
Info: Fitter routing operations ending: elapsed time is 00:00:17
Info: The Fitter performed an Auto Fit compilation.  No optimizations were skipped because the design's timing and routability requirements required full optimization.
Info: Completed Fixed Delay Chain Operation
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Completed Auto Delay Chain Operation
Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
Info: Quartus II Fitter was successful. 0 errors, 0 warnings
    Info: Allocated 171 megabytes of memory during processing
    Info: Processing ended: Tue Jun 12 11:12:31 2007
    Info: Elapsed time: 00:01:31