top.map.summary

来自「RS编码的verilog源代码」· SUMMARY 代码 · 共 11 行

SUMMARY
11
字号
Analysis & Synthesis Status : Successful - Wed Jun 13 09:43:29 2007
Quartus II Version : 5.1 Build 216 03/06/2006 SP 2 SJ Full Version
Revision Name : top
Top-level Entity Name : rs
Family : Cyclone
Total logic elements : 1,697
Total pins : 11
Total virtual pins : 0
Total memory bits : 480
Total PLLs : 1

⌨️ 快捷键说明

复制代码Ctrl + C
搜索代码Ctrl + F
全屏模式F11
增大字号Ctrl + =
减小字号Ctrl + -
显示快捷键?