serial_paralled_conversion.v

RS编码的verilog源代码

module Dec2Bit(reset,start,clkin,in,clkout,out,outstart);
input reset,clkin,start,clkout;
input[4:0] in;
reg[4:0] buff;
output out;
reg out;
reg[2:0] cnt;
output outstart;
reg enable,outstart;

always @ (negedge start or negedge reset)
begin
if(~reset) enable=0;
else   enable=1;
end

always @ (posedge clkout or negedge reset )
begin
    if(~reset)
    begin
       cnt=0;
       out=0;
       outstart=0;
    end
    else if(enable)
    begin
    if(cnt==0)
       outstart=1;
    else outstart=0;
    if(cnt==1)
       buff=in;
    if(cnt>=5)
       cnt<=1;
    else
       cnt<=cnt+1;
    case(cnt)
         1:out<=buff[4];
         2:out<=buff[3];
         3:out<=buff[2];
         4:out<=buff[1];
         5:out<=buff[0];
    endcase
    end
end
endmodule


module Bit2Dec(reset,start,clkin,in,clkout,out,outstart);
input reset,start,clkin,in,clkout;
output[4:0] out;
reg[4:0] out;
reg c1,c2,c3,c4,c5;
reg[2:0] cnt;
output outstart;
reg enable,outstart;

always @ (negedge start or negedge reset)
begin
if(~reset) enable=0;
else   enable=1;
end
always @ (posedge clkin or negedge reset)
    begin
    if(~reset)
    begin
       cnt=0;
       out=0;
       outstart=0;
    end
    else if(enable)
    begin
         c2<=c1;
	     c3<=c2;
	     c4<=c3;
	     c5<=c4;
	     c1<=in;
		 if(cnt==0)
		 outstart=1;
	     if(cnt==5)
	         begin
			 outstart=0;
	         out[0]<=c1 ;
             out[1]<=c2 ;
             out[2]<=c3 ; 
             out[3]<=c4 ;
             out[4]<=c5 ;
             cnt<=1;
             end
          else
             cnt<=cnt+1;	         
    end
     end 
endmodule