12位寄存器.v

计数器 锁存器 12位寄存器 带load

// User-Defined Macrofunction
// download from: http://www.fpga.com.cn 


module reg12 ( d, clk, q);

input [11:0]d;
input clk;
output [11:0]q;

reg [11:0]q;

always @(posedge clk)
     q = d;

endmodule