clk_div5.tan.qmsg

对任意始终进行精确的5分频处理,而且没有毛刺,效果很好.

{ "Info" "ITDB_FULL_SLACK_RESULT" "clk register countr\[0\] register levelr 48.401 ns " "Info: Slack time is 48.401 ns for clock \"clk\" between source register \"countr\[0\]\" and destination register \"levelr\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT_RESTRICTED" "275.03 MHz " "Info: Fmax is restricted to 275.03 MHz due to tcl and tch limits" {  } {  } 0 0 "Fmax is restricted to %1!s! due to tcl and tch limits" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "49.739 ns + Largest register register " "Info: + Largest register to register requirement is 49.739 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "50.000 ns + " "Info: + Setup relationship between source and destination is 50.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 50.000 ns " "Info: + Latch edge is 50.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination clk 50.000 ns 0.000 ns  50 " "Info: Clock period of Destination clock \"clk\" is 50.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source clk 50.000 ns 0.000 ns  50 " "Info: Clock period of Source clock \"clk\" is 50.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0}  } {  } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Largest " "Info: + Largest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.730 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.730 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_17 8 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 8; CLK Node = 'clk'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "clk_div5" "UNKNOWN" "V1" "D:/fpga例子/clk_div5/db/clk_div5.quartus_db" { Floorplan "D:/fpga例子/clk_div5/" "" "" { clk } "NODE_NAME" } "" } } { "clk_div5.vhd" "" { Text "D:/fpga例子/clk_div5/clk_div5.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.711 ns) 2.730 ns levelr 2 REG LC_X1_Y4_N7 2 " "Info: 2: + IC(0.550 ns) + CELL(0.711 ns) = 2.730 ns; Loc. = LC_X1_Y4_N7; Fanout = 2; REG Node = 'levelr'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "clk_div5" "UNKNOWN" "V1" "D:/fpga例子/clk_div5/db/clk_div5.quartus_db" { Floorplan "D:/fpga例子/clk_div5/" "" "1.261 ns" { clk levelr } "NODE_NAME" } "" } } { "clk_div5.vhd" "" { Text "D:/fpga例子/clk_div5/clk_div5.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 79.85 % ) " "Info: Total cell delay = 2.180 ns ( 79.85 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.550 ns ( 20.15 % ) " "Info: Total interconnect delay = 0.550 ns ( 20.15 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "clk_div5" "UNKNOWN" "V1" "D:/fpga例子/clk_div5/db/clk_div5.quartus_db" { Floorplan "D:/fpga例子/clk_div5/" "" "2.730 ns" { clk levelr } "NODE_NAME" } "" } } { "d:/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/bin/Technology_Viewer.qrui" "2.730 ns" { clk clk~out0 levelr } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.730 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.730 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_17 8 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 8; CLK Node = 'clk'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "clk_div5" "UNKNOWN" "V1" "D:/fpga例子/clk_div5/db/clk_div5.quartus_db" { Floorplan "D:/fpga例子/clk_div5/" "" "" { clk } "NODE_NAME" } "" } } { "clk_div5.vhd" "" { Text "D:/fpga例子/clk_div5/clk_div5.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.711 ns) 2.730 ns countr\[0\] 2 REG LC_X1_Y4_N2 4 " "Info: 2: + IC(0.550 ns) + CELL(0.711 ns) = 2.730 ns; Loc. = LC_X1_Y4_N2; Fanout = 4; REG Node = 'countr\[0\]'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "clk_div5" "UNKNOWN" "V1" "D:/fpga例子/clk_div5/db/clk_div5.quartus_db" { Floorplan "D:/fpga例子/clk_div5/" "" "1.261 ns" { clk countr[0] } "NODE_NAME" } "" } } { "clk_div5.vhd" "" { Text "D:/fpga例子/clk_div5/clk_div5.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 79.85 % ) " "Info: Total cell delay = 2.180 ns ( 79.85 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.550 ns ( 20.15 % ) " "Info: Total interconnect delay = 0.550 ns ( 20.15 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "clk_div5" "UNKNOWN" "V1" "D:/fpga例子/clk_div5/db/clk_div5.quartus_db" { Floorplan "D:/fpga例子/clk_div5/" "" "2.730 ns" { clk countr[0] } "NODE_NAME" } "" } } { "d:/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/bin/Technology_Viewer.qrui" "2.730 ns" { clk clk~out0 countr[0] } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "clk_div5" "UNKNOWN" "V1" "D:/fpga例子/clk_div5/db/clk_div5.quartus_db" { Floorplan "D:/fpga例子/clk_div5/" "" "2.730 ns" { clk levelr } "NODE_NAME" } "" } } { "d:/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/bin/Technology_Viewer.qrui" "2.730 ns" { clk clk~out0 levelr } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "clk_div5" "UNKNOWN" "V1" "D:/fpga例子/clk_div5/db/clk_div5.quartus_db" { Floorplan "D:/fpga例子/clk_div5/" "" "2.730 ns" { clk countr[0] } "NODE_NAME" } "" } } { "d:/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/bin/Technology_Viewer.qrui" "2.730 ns" { clk clk~out0 countr[0] } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "clk_div5.vhd" "" { Text "D:/fpga例子/clk_div5/clk_div5.vhd" 20 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns - " "Info: - Micro setup delay of destination is 0.037 ns" {  } { { "clk_div5.vhd" "" { Text "D:/fpga例子/clk_div5/clk_div5.vhd" 15 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "clk_div5" "UNKNOWN" "V1" "D:/fpga例子/clk_div5/db/clk_div5.quartus_db" { Floorplan "D:/fpga例子/clk_div5/" "" "2.730 ns" { clk levelr } "NODE_NAME" } "" } } { "d:/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/bin/Technology_Viewer.qrui" "2.730 ns" { clk clk~out0 levelr } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "clk_div5" "UNKNOWN" "V1" "D:/fpga例子/clk_div5/db/clk_div5.quartus_db" { Floorplan "D:/fpga例子/clk_div5/" "" "2.730 ns" { clk countr[0] } "NODE_NAME" } "" } } { "d:/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/bin/Technology_Viewer.qrui" "2.730 ns" { clk clk~out0 countr[0] } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.338 ns - Longest register register " "Info: - Longest register to register delay is 1.338 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns countr\[0\] 1 REG LC_X1_Y4_N2 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y4_N2; Fanout = 4; REG Node = 'countr\[0\]'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "clk_div5" "UNKNOWN" "V1" "D:/fpga例子/clk_div5/db/clk_div5.quartus_db" { Floorplan "D:/fpga例子/clk_div5/" "" "" { countr[0] } "NODE_NAME" } "" } } { "clk_div5.vhd" "" { Text "D:/fpga例子/clk_div5/clk_div5.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(0.738 ns) 1.338 ns levelr 2 REG LC_X1_Y4_N7 2 " "Info: 2: + IC(0.600 ns) + CELL(0.738 ns) = 1.338 ns; Loc. = LC_X1_Y4_N7; Fanout = 2; REG Node = 'levelr'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "clk_div5" "UNKNOWN" "V1" "D:/fpga例子/clk_div5/db/clk_div5.quartus_db" { Floorplan "D:/fpga例子/clk_div5/" "" "1.338 ns" { countr[0] levelr } "NODE_NAME" } "" } } { "clk_div5.vhd" "" { Text "D:/fpga例子/clk_div5/clk_div5.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.738 ns ( 55.16 % ) " "Info: Total cell delay = 0.738 ns ( 55.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.600 ns ( 44.84 % ) " "Info: Total interconnect delay = 0.600 ns ( 44.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "clk_div5" "UNKNOWN" "V1" "D:/fpga例子/clk_div5/db/clk_div5.quartus_db" { Floorplan "D:/fpga例子/clk_div5/" "" "1.338 ns" { countr[0] levelr } "NODE_NAME" } "" } } { "d:/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/bin/Technology_Viewer.qrui" "1.338 ns" { countr[0] levelr } { 0.000ns 0.600ns } { 0.000ns 0.738ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "clk_div5" "UNKNOWN" "V1" "D:/fpga例子/clk_div5/db/clk_div5.quartus_db" { Floorplan "D:/fpga例子/clk_div5/" "" "2.730 ns" { clk levelr } "NODE_NAME" } "" } } { "d:/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/bin/Technology_Viewer.qrui" "2.730 ns" { clk clk~out0 levelr } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "clk_div5" "UNKNOWN" "V1" "D:/fpga例子/clk_div5/db/clk_div5.quartus_db" { Floorplan "D:/fpga例子/clk_div5/" "" "2.730 ns" { clk countr[0] } "NODE_NAME" } "" } } { "d:/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/bin/Technology_Viewer.qrui" "2.730 ns" { clk clk~out0 countr[0] } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "clk_div5" "UNKNOWN" "V1" "D:/fpga例子/clk_div5/db/clk_div5.quartus_db" { Floorplan "D:/fpga例子/clk_div5/" "" "1.338 ns" { countr[0] levelr } "NODE_NAME" } "" } } { "d:/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/bin/Technology_Viewer.qrui" "1.338 ns" { countr[0] levelr } { 0.000ns 0.600ns } { 0.000ns 0.738ns } } }  } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "clk register levelf register levelf 1.047 ns " "Info: Minimum slack time is 1.047 ns for clock \"clk\" between source register \"levelf\" and destination register \"levelf\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.838 ns + Shortest register register " "Info: + Shortest register to register delay is 0.838 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns levelf 1 REG LC_X1_Y4_N3 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y4_N3; Fanout = 2; REG Node = 'levelf'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "clk_div5" "UNKNOWN" "V1" "D:/fpga例子/clk_div5/db/clk_div5.quartus_db" { Floorplan "D:/fpga例子/clk_div5/" "" "" { levelf } "NODE_NAME" } "" } } { "clk_div5.vhd" "" { Text "D:/fpga例子/clk_div5/clk_div5.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.529 ns) + CELL(0.309 ns) 0.838 ns levelf 2 REG LC_X1_Y4_N3 2 " "Info: 2: + IC(0.529 ns) + CELL(0.309 ns) = 0.838 ns; Loc. = LC_X1_Y4_N3; Fanout = 2; REG Node = 'levelf'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "clk_div5" "UNKNOWN" "V1" "D:/fpga例子/clk_div5/db/clk_div5.quartus_db" { Floorplan "D:/fpga例子/clk_div5/" "" "0.838 ns" { levelf levelf } "NODE_NAME" } "" } } { "clk_div5.vhd" "" { Text "D:/fpga例子/clk_div5/clk_div5.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.309 ns ( 36.87 % ) " "Info: Total cell delay = 0.309 ns ( 36.87 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.529 ns ( 63.13 % ) " "Info: Total interconnect delay = 0.529 ns ( 63.13 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "clk_div5" "UNKNOWN" "V1" "D:/fpga例子/clk_div5/db/clk_div5.quartus_db" { Floorplan "D:/fpga例子/clk_div5/" "" "0.838 ns" { levelf levelf } "NODE_NAME" } "" } } { "d:/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/bin/Technology_Viewer.qrui" "0.838 ns" { levelf levelf } { 0.000ns 0.529ns } { 0.000ns 0.309ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "-0.209 ns - Smallest register register " "Info: - Smallest register to register requirement is -0.209 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 25.000 ns " "Info: + Latch edge is 25.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination clk 50.000 ns 25.000 ns inverted 50 " "Info: Clock period of Destination clock \"clk\" is 50.000 ns with inverted offset of 25.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 25.000 ns " "Info: - Launch edge is 25.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source clk 50.000 ns 25.000 ns inverted 50 " "Info: Clock period of Source clock \"clk\" is 50.000 ns with inverted offset of 25.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0}  } {  } 0 0 "%2!c! Hold relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.730 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.730 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_17 8 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 8; CLK Node = 'clk'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "clk_div5" "UNKNOWN" "V1" "D:/fpga例子/clk_div5/db/clk_div5.quartus_db" { Floorplan "D:/fpga例子/clk_div5/" "" "" { clk } "NODE_NAME" } "" } } { "clk_div5.vhd" "" { Text "D:/fpga例子/clk_div5/clk_div5.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.711 ns) 2.730 ns levelf 2 REG LC_X1_Y4_N3 2 " "Info: 2: + IC(0.550 ns) + CELL(0.711 ns) = 2.730 ns; Loc. = LC_X1_Y4_N3; Fanout = 2; REG Node = 'levelf'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "clk_div5" "UNKNOWN" "V1" "D:/fpga例子/clk_div5/db/clk_div5.quartus_db" { Floorplan "D:/fpga例子/clk_div5/" "" "1.261 ns" { clk levelf } "NODE_NAME" } "" } } { "clk_div5.vhd" "" { Text "D:/fpga例子/clk_div5/clk_div5.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 79.85 % ) " "Info: Total cell delay = 2.180 ns ( 79.85 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.550 ns ( 20.15 % ) " "Info: Total interconnect delay = 0.550 ns ( 20.15 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "clk_div5" "UNKNOWN" "V1" "D:/fpga例子/clk_div5/db/clk_div5.quartus_db" { Floorplan "D:/fpga例子/clk_div5/" "" "2.730 ns" { clk levelf } "NODE_NAME" } "" } } { "d:/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/bin/Technology_Viewer.qrui" "2.730 ns" { clk clk~out0 levelf } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.730 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 2.730 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_17 8 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 8; CLK Node = 'clk'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "clk_div5" "UNKNOWN" "V1" "D:/fpga例子/clk_div5/db/clk_div5.quartus_db" { Floorplan "D:/fpga例子/clk_div5/" "" "" { clk } "NODE_NAME" } "" } } { "clk_div5.vhd" "" { Text "D:/fpga例子/clk_div5/clk_div5.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.711 ns) 2.730 ns levelf 2 REG LC_X1_Y4_N3 2 " "Info: 2: + IC(0.550 ns) + CELL(0.711 ns) = 2.730 ns; Loc. = LC_X1_Y4_N3; Fanout = 2; REG Node = 'levelf'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "clk_div5" "UNKNOWN" "V1" "D:/fpga例子/clk_div5/db/clk_div5.quartus_db" { Floorplan "D:/fpga例子/clk_div5/" "" "1.261 ns" { clk levelf } "NODE_NAME" } "" } } { "clk_div5.vhd" "" { Text "D:/fpga例子/clk_div5/clk_div5.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 79.85 % ) " "Info: Total cell delay = 2.180 ns ( 79.85 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.550 ns ( 20.15 % ) " "Info: Total interconnect delay = 0.550 ns ( 20.15 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "clk_div5" "UNKNOWN" "V1" "D:/fpga例子/clk_div5/db/clk_div5.quartus_db" { Floorplan "D:/fpga例子/clk_div5/" "" "2.730 ns" { clk levelf } "NODE_NAME" } "" } } { "d:/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/bin/Technology_Viewer.qrui" "2.730 ns" { clk clk~out0 levelf } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "clk_div5" "UNKNOWN" "V1" "D:/fpga例子/clk_div5/db/clk_div5.quartus_db" { Floorplan "D:/fpga例子/clk_div5/" "" "2.730 ns" { clk levelf } "NODE_NAME" } "" } } { "d:/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/bin/Technology_Viewer.qrui" "2.730 ns" { clk clk~out0 levelf } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "clk_div5" "UNKNOWN" "V1" "D:/fpga例子/clk_div5/db/clk_div5.quartus_db" { Floorplan "D:/fpga例子/clk_div5/" "" "2.730 ns" { clk levelf } "NODE_NAME" } "" } } { "d:/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/bin/Technology_Viewer.qrui" "2.730 ns" { clk clk~out0 levelf } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "clk_div5.vhd" "" { Text "D:/fpga例子/clk_div5/clk_div5.vhd" 16 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "clk_div5.vhd" "" { Text "D:/fpga例子/clk_div5/clk_div5.vhd" 16 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0}  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "clk_div5" "UNKNOWN" "V1" "D:/fpga例子/clk_div5/db/clk_div5.quartus_db" { Floorplan "D:/fpga例子/clk_div5/" "" "2.730 ns" { clk levelf } "NODE_NAME" } "" } } { "d:/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/bin/Technology_Viewer.qrui" "2.730 ns" { clk clk~out0 levelf } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "clk_div5" "UNKNOWN" "V1" "D:/fpga例子/clk_div5/db/clk_div5.quartus_db" { Floorplan "D:/fpga例子/clk_div5/" "" "2.730 ns" { clk levelf } "NODE_NAME" } "" } } { "d:/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/bin/Technology_Viewer.qrui" "2.730 ns" { clk clk~out0 levelf } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0}  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "clk_div5" "UNKNOWN" "V1" "D:/fpga例子/clk_div5/db/clk_div5.quartus_db" { Floorplan "D:/fpga例子/clk_div5/" "" "0.838 ns" { levelf levelf } "NODE_NAME" } "" } } { "d:/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/bin/Technology_Viewer.qrui" "0.838 ns" { levelf levelf } { 0.000ns 0.529ns } { 0.000ns 0.309ns } } } { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "clk_div5" "UNKNOWN" "V1" "D:/fpga例子/clk_div5/db/clk_div5.quartus_db" { Floorplan "D:/fpga例子/clk_div5/" "" "2.730 ns" { clk levelf } "NODE_NAME" } "" } } { "d:/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/bin/Technology_Viewer.qrui" "2.730 ns" { clk clk~out0 levelf } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "clk_div5" "UNKNOWN" "V1" "D:/fpga例子/clk_div5/db/clk_div5.quartus_db" { Floorplan "D:/fpga例子/clk_div5/" "" "2.730 ns" { clk levelf } "NODE_NAME" } "" } } { "d:/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/bin/Technology_Viewer.qrui" "2.730 ns" { clk clk~out0 levelf } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "Minimum slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk clk_div levelr 7.050 ns register " "Info: tco from clock \"clk\" to destination pin \"clk_div\" through register \"levelr\" is 7.050 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.730 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.730 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_17 8 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 8; CLK Node = 'clk'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "clk_div5" "UNKNOWN" "V1" "D:/fpga例子/clk_div5/db/clk_div5.quartus_db" { Floorplan "D:/fpga例子/clk_div5/" "" "" { clk } "NODE_NAME" } "" } } { "clk_div5.vhd" "" { Text "D:/fpga例子/clk_div5/clk_div5.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.711 ns) 2.730 ns levelr 2 REG LC_X1_Y4_N7 2 " "Info: 2: + IC(0.550 ns) + CELL(0.711 ns) = 2.730 ns; Loc. = LC_X1_Y4_N7; Fanout = 2; REG Node = 'levelr'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "clk_div5" "UNKNOWN" "V1" "D:/fpga例子/clk_div5/db/clk_div5.quartus_db" { Floorplan "D:/fpga例子/clk_div5/" "" "1.261 ns" { clk levelr } "NODE_NAME" } "" } } { "clk_div5.vhd" "" { Text "D:/fpga例子/clk_div5/clk_div5.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 79.85 % ) " "Info: Total cell delay = 2.180 ns ( 79.85 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.550 ns ( 20.15 % ) " "Info: Total interconnect delay = 0.550 ns ( 20.15 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "clk_div5" "UNKNOWN" "V1" "D:/fpga例子/clk_div5/db/clk_div5.quartus_db" { Floorplan "D:/fpga例子/clk_div5/" "" "2.730 ns" { clk levelr } "NODE_NAME" } "" } } { "d:/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/bin/Technology_Viewer.qrui" "2.730 ns" { clk clk~out0 levelr } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "clk_div5.vhd" "" { Text "D:/fpga例子/clk_div5/clk_div5.vhd" 15 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.096 ns + Longest register pin " "Info: + Longest register to pin delay is 4.096 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns levelr 1 REG LC_X1_Y4_N7 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y4_N7; Fanout = 2; REG Node = 'levelr'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "clk_div5" "UNKNOWN" "V1" "D:/fpga例子/clk_div5/db/clk_div5.quartus_db" { Floorplan "D:/fpga例子/clk_div5/" "" "" { levelr } "NODE_NAME" } "" } } { "clk_div5.vhd" "" { Text "D:/fpga例子/clk_div5/clk_div5.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.587 ns) + CELL(0.292 ns) 0.879 ns clk_div~0 2 COMB LC_X1_Y4_N5 1 " "Info: 2: + IC(0.587 ns) + CELL(0.292 ns) = 0.879 ns; Loc. = LC_X1_Y4_N5; Fanout = 1; COMB Node = 'clk_div~0'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "clk_div5" "UNKNOWN" "V1" "D:/fpga例子/clk_div5/db/clk_div5.quartus_db" { Floorplan "D:/fpga例子/clk_div5/" "" "0.879 ns" { levelr clk_div~0 } "NODE_NAME" } "" } } { "clk_div5.vhd" "" { Text "D:/fpga例子/clk_div5/clk_div5.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.093 ns) + CELL(2.124 ns) 4.096 ns clk_div 3 PIN PIN_27 0 " "Info: 3: + IC(1.093 ns) + CELL(2.124 ns) = 4.096 ns; Loc. = PIN_27; Fanout = 0; PIN Node = 'clk_div'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "clk_div5" "UNKNOWN" "V1" "D:/fpga例子/clk_div5/db/clk_div5.quartus_db" { Floorplan "D:/fpga例子/clk_div5/" "" "3.217 ns" { clk_div~0 clk_div } "NODE_NAME" } "" } } { "clk_div5.vhd" "" { Text "D:/fpga例子/clk_div5/clk_div5.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.416 ns ( 58.98 % ) " "Info: Total cell delay = 2.416 ns ( 58.98 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.680 ns ( 41.02 % ) " "Info: Total interconnect delay = 1.680 ns ( 41.02 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "clk_div5" "UNKNOWN" "V1" "D:/fpga例子/clk_div5/db/clk_div5.quartus_db" { Floorplan "D:/fpga例子/clk_div5/" "" "4.096 ns" { levelr clk_div~0 clk_div } "NODE_NAME" } "" } } { "d:/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/bin/Technology_Viewer.qrui" "4.096 ns" { levelr clk_div~0 clk_div } { 0.000ns 0.587ns 1.093ns } { 0.000ns 0.292ns 2.124ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "clk_div5" "UNKNOWN" "V1" "D:/fpga例子/clk_div5/db/clk_div5.quartus_db" { Floorplan "D:/fpga例子/clk_div5/" "" "2.730 ns" { clk levelr } "NODE_NAME" } "" } } { "d:/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/bin/Technology_Viewer.qrui" "2.730 ns" { clk clk~out0 levelr } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "clk_div5" "UNKNOWN" "V1" "D:/fpga例子/clk_div5/db/clk_div5.quartus_db" { Floorplan "D:/fpga例子/clk_div5/" "" "4.096 ns" { levelr clk_div~0 clk_div } "NODE_NAME" } "" } } { "d:/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/bin/Technology_Viewer.qrui" "4.096 ns" { levelr clk_div~0 clk_div } { 0.000ns 0.587ns 1.093ns } { 0.000ns 0.292ns 2.124ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}