latch_if2.v

来自「Vlerilog HDL高级数字设计源码」· Verilog 代码 · 共 11 行

module latch_if2 (data_out, data_in, latch_enable);
  output	[3: 0] 	data_out; 
  input 	[3: 0] 	data_in;
  input 		latch_enable;
  reg 	[3: 0] 	data_out;
 
  always @  (latch_enable or data_in)
    if (latch_enable) data_out = data_in;	// Incompletely specified	
endmodule