clock.v

来自「Vlerilog HDL高级数字设计源码」· Verilog 代码 · 共 15 行

module clock_gen (clock);
  parameter Half_cycle = 50;
  output clock;
  reg clock;

  initial
    clock = 0;

  always
    begin
      # Half_cycle clock = ~ clock;
    end
endmodule