bmul32_test.vhdl

32位并行乘法器的测试文件

-- bmul32_test.vhdl   test entity bmul32

--signal a[32];  multiplier
--signal b[32];  multiplicand
--signal c[64];  product

library STD;
use STD.textio.all;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_textio.all;
use IEEE.std_logic_arith.all;

entity bmul32_test is
end bmul32_test;

architecture circuits of bmul32_test is
  signal cntr : std_logic_vector(3 downto 0) := B"0001";
  signal a    : std_logic_vector(31 downto 0) := X"00000000";
  signal b    : std_logic_vector(31 downto 0) := X"00000000";
  signal prod : std_logic_vector(63 downto 0);

  procedure my_printout(a   : std_logic_vector(31 downto 0);
                        b   : std_logic_vector(31 downto 0);
                        prod: std_logic_vector(63 downto 0)) is
    variable my_line : line;
    alias swrite is write [line, string, side, width] ;
  begin
    swrite(my_line, "a=");
    hwrite(my_line, a);
    swrite(my_line, ", b=");
    hwrite(my_line, b);
    swrite(my_line, ",  prod=");
    hwrite(my_line, prod);
    swrite(my_line, ", cntr=");
    write(my_line, cntr);
    swrite(my_line, ",  at=");
    write(my_line, now);
    writeline(output, my_line);
    writeline(output, my_line); -- blank line
  end my_printout;
  
begin  -- circuits of bmul32_test
  mult32: entity WORK.bmul32 port map(a, b, prod); -- parallel circuit
  driver: process                      -- serial code
            variable my_line : LINE;
          begin  -- process driver
            write(my_line, string'("Driver starting."));
            writeline(output, my_line);
            
            for i in 0 to 4 loop

              a( 3 downto  0) <= cntr; -- or "0001";
              a( 7 downto  4) <= cntr;
              a(11 downto  8) <= cntr;
              a(15 downto 12) <= cntr;
              a(19 downto 16) <= cntr;
              a(23 downto 20) <= cntr;
              a(27 downto 24) <= cntr;
              a(31 downto 28) <= cntr;
              b( 3 downto  0) <= cntr;
              b( 7 downto  4) <= cntr;
              b(11 downto  8) <= cntr;
              b(15 downto 12) <= cntr;
              b(19 downto 16) <= cntr;
              b(23 downto 20) <= cntr;
              b(27 downto 24) <= cntr;
              b(31 downto 28) <= cntr;

              wait for 319 ns;  -- pseudo clock wait for propogation
              my_printout(a, b, prod);  -- write output
              cntr <= unsigned(cntr) + unsigned(cntr);
              wait for 1 ns;
            end loop;  -- i
            a <= x"FFFFFFFF";
            b <= x"FFFFFFFF";
            wait for 319 ns;  -- pseudo clock wait for propogation
            my_printout(a, b, prod);  -- write output
            cntr <= unsigned(cntr) + unsigned(cntr);
            a <= x"7FFFFFFF";
            b <= x"7FFFFFFF";
            wait for 319 ns;  -- pseudo clock wait for propogation
            my_printout(a, b, prod);  -- write output
            cntr <= unsigned(cntr) + unsigned(cntr);
          end process driver;
end architecture circuits; -- of bmul32_test