dffl.vhd

VHDL计数器功能从００００到ffff记数

library ieee;
  use ieee.std_logic_1164.all;
  entity dffl is
     port ( rst ,clk: in std_logic;
            d :  in std_logic;
           q ,nq :out std_logic );
     end;
    architecture bhv of dffl is
    signal q1 , nq1 :std_logic;
    begin
       process(clk,rst) is 
        begin
        if rst='0' then q1<='0';nq1<='1';
        elsif clk'event and clk='1' then
              q1 <= d;
              nq1 <=not d;
        end if ;
        q<=q1;
        nq<=nq1;
        end process;
     end;