jsq_d.vhd

VHDL计数器功能从００００到ffff记数

library ieee;
use ieee.std_logic_1164.all;
entity jsq_d is 
 port (rst ,clk , clk1 :in std_logic;
       q3 ,q2 ,q1 ,q0 ,nq3 ,nq2 ,nq1 ,nq0 :out std_logic;
       sm ,sm_1 , sm_2 ,sm_3 : out std_logic_vector (3 downto 0));
 end;
architecture bh of jsq_d is
component dffl is
port (clk ,rst :in std_logic;
      d :in std_logic;
      q , nq : out std_logic);
end component dffl;
signal q_3,nq_3 ,q_2 ,nq_2 ,q_1 ,nq_1 ,q_0 ,nq_0 :std_logic;
signal aa:std_logic_vector (3 downto 0);
begin 
  process(clk1) is
  begin
  if clk1'event and clk1='1' then
  aa<=q_3&q_2&q_1&q_0;
  sm <=aa;
  sm_1 <= aa;
  sm_2 <= aa;
  sm_3 <= aa;
  end if;
 end process;
nq3<=nq_3;
q3<=q_3;
nq2<=nq_2;
q2<=q_2;
nq1<=nq_1;
q1<=q_1;
nq0<=nq_0;
q0<=q_0;
u1:dffl port map(rst=>rst, clk=>clk, d=>nq_0, q=>q_0, nq=>nq_0);
u2:dffl port map(rst=>rst, clk=>nq_0, d=>nq_1, q=>q_1, nq=>nq_1);
u3:dffl port map(rst=>rst, clk=>nq_1, d=>nq_2, q=>q_2, nq=>nq_2);
u4:dffl port map(rst=>rst, clk=>nq_2, d=>nq_3, q=>q_3, nq=>nq_3);
end;