📄 jsq_d.rpt
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LC22 -> - - - - - - - - - - - * | * - | <-- q0
LC19 -> - - - - - - - - - - * - | * - | <-- q1
LC18 -> - - - - - - - - - * - - | * - | <-- q2
LC17 -> - - - - - - - - * - - - | * - | <-- q3
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: c:\max\shiyan5\jsq\jsq_d.rpt
jsq_d
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+------------------------------- LC24 nq0
| +----------------------------- LC23 nq1
| | +--------------------------- LC20 nq2
| | | +------------------------- LC21 nq3
| | | | +----------------------- LC22 q0
| | | | | +--------------------- LC19 q1
| | | | | | +------------------- LC18 q2
| | | | | | | +----------------- LC17 q3
| | | | | | | | +--------------- LC31 sm0
| | | | | | | | | +------------- LC32 sm1
| | | | | | | | | | +----------- LC30 sm_10
| | | | | | | | | | | +--------- LC25 sm_11
| | | | | | | | | | | | +------- LC26 sm_20
| | | | | | | | | | | | | +----- LC27 sm_21
| | | | | | | | | | | | | | +--- LC28 sm_30
| | | | | | | | | | | | | | | +- LC29 sm_31
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | | | | | A B | Logic cells that feed LAB 'B':
LC24 -> * * - - * * - - - - - - - - - - | - * | <-- nq0
LC23 -> - * * - - * * - - - - - - - - - | - * | <-- nq1
LC20 -> - - * * - - * * - - - - - - - - | - * | <-- nq2
LC21 -> - - - * - - - * - - - - - - - - | - * | <-- nq3
Pin
4 -> * - - - * - - - - - - - - - - - | - * | <-- clk
43 -> - - - - - - - - - - - - - - - - | - - | <-- clk1
5 -> * * * * * * * * - - - - - - - - | - * | <-- rst
LC10 -> - - - - - - - - - * - * - * - * | - * | <-- aa1
LC14 -> - - - - - - - - * - * - * - * - | - * | <-- aa0
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: c:\max\shiyan5\jsq\jsq_d.rpt
jsq_d
** EQUATIONS **
clk : INPUT;
clk1 : INPUT;
rst : INPUT;
-- Node name is ':51' = 'aa0'
-- Equation name is 'aa0', location is LC014, type is buried.
aa0 = DFFE( q0 $ GND, GLOBAL( clk1), VCC, VCC, VCC);
-- Node name is ':50' = 'aa1'
-- Equation name is 'aa1', location is LC010, type is buried.
aa1 = DFFE( q1 $ GND, GLOBAL( clk1), VCC, VCC, VCC);
-- Node name is ':49' = 'aa2'
-- Equation name is 'aa2', location is LC012, type is buried.
aa2 = DFFE( q2 $ GND, GLOBAL( clk1), VCC, VCC, VCC);
-- Node name is ':48' = 'aa3'
-- Equation name is 'aa3', location is LC013, type is buried.
aa3 = DFFE( q3 $ GND, GLOBAL( clk1), VCC, VCC, VCC);
-- Node name is 'nq0' = '|dffl:u1|nq1'
-- Equation name is 'nq0', type is output
nq0 = TFFE( VCC, clk, VCC, rst, VCC);
-- Node name is 'nq1' = '|dffl:u2|nq1'
-- Equation name is 'nq1', type is output
nq1 = TFFE( VCC, nq0, VCC, rst, VCC);
-- Node name is 'nq2' = '|dffl:u3|nq1'
-- Equation name is 'nq2', type is output
nq2 = TFFE( VCC, nq1, VCC, rst, VCC);
-- Node name is 'nq3' = '|dffl:u4|nq1'
-- Equation name is 'nq3', type is output
nq3 = TFFE( VCC, nq2, VCC, rst, VCC);
-- Node name is 'q0' = '|dffl:u1|q1'
-- Equation name is 'q0', type is output
q0 = DFFE( nq0 $ GND, clk, rst, VCC, VCC);
-- Node name is 'q1' = '|dffl:u2|q1'
-- Equation name is 'q1', type is output
q1 = DFFE( nq1 $ GND, nq0, rst, VCC, VCC);
-- Node name is 'q2' = '|dffl:u3|q1'
-- Equation name is 'q2', type is output
q2 = DFFE( nq2 $ GND, nq1, rst, VCC, VCC);
-- Node name is 'q3' = '|dffl:u4|q1'
-- Equation name is 'q3', type is output
q3 = DFFE( nq3 $ GND, nq2, rst, VCC, VCC);
-- Node name is 'sm0' = ':18'
-- Equation name is 'sm0', type is output
sm0 = DFFE( aa0 $ GND, GLOBAL( clk1), VCC, VCC, VCC);
-- Node name is 'sm1' = ':16'
-- Equation name is 'sm1', type is output
sm1 = DFFE( aa1 $ GND, GLOBAL( clk1), VCC, VCC, VCC);
-- Node name is 'sm2' = ':14'
-- Equation name is 'sm2', type is output
sm2 = DFFE( aa2 $ GND, GLOBAL( clk1), VCC, VCC, VCC);
-- Node name is 'sm3' = ':12'
-- Equation name is 'sm3', type is output
sm3 = DFFE( aa3 $ GND, GLOBAL( clk1), VCC, VCC, VCC);
-- Node name is 'sm_10' = ':26'
-- Equation name is 'sm_10', type is output
sm_10 = DFFE( aa0 $ GND, GLOBAL( clk1), VCC, VCC, VCC);
-- Node name is 'sm_11' = ':24'
-- Equation name is 'sm_11', type is output
sm_11 = DFFE( aa1 $ GND, GLOBAL( clk1), VCC, VCC, VCC);
-- Node name is 'sm_12' = ':22'
-- Equation name is 'sm_12', type is output
sm_12 = DFFE( aa2 $ GND, GLOBAL( clk1), VCC, VCC, VCC);
-- Node name is 'sm_13' = ':20'
-- Equation name is 'sm_13', type is output
sm_13 = DFFE( aa3 $ GND, GLOBAL( clk1), VCC, VCC, VCC);
-- Node name is 'sm_20' = ':34'
-- Equation name is 'sm_20', type is output
sm_20 = DFFE( aa0 $ GND, GLOBAL( clk1), VCC, VCC, VCC);
-- Node name is 'sm_21' = ':32'
-- Equation name is 'sm_21', type is output
sm_21 = DFFE( aa1 $ GND, GLOBAL( clk1), VCC, VCC, VCC);
-- Node name is 'sm_22' = ':30'
-- Equation name is 'sm_22', type is output
sm_22 = DFFE( aa2 $ GND, GLOBAL( clk1), VCC, VCC, VCC);
-- Node name is 'sm_23' = ':28'
-- Equation name is 'sm_23', type is output
sm_23 = DFFE( aa3 $ GND, GLOBAL( clk1), VCC, VCC, VCC);
-- Node name is 'sm_30' = ':42'
-- Equation name is 'sm_30', type is output
sm_30 = DFFE( aa0 $ GND, GLOBAL( clk1), VCC, VCC, VCC);
-- Node name is 'sm_31' = ':40'
-- Equation name is 'sm_31', type is output
sm_31 = DFFE( aa1 $ GND, GLOBAL( clk1), VCC, VCC, VCC);
-- Node name is 'sm_32' = ':38'
-- Equation name is 'sm_32', type is output
sm_32 = DFFE( aa2 $ GND, GLOBAL( clk1), VCC, VCC, VCC);
-- Node name is 'sm_33' = ':36'
-- Equation name is 'sm_33', type is output
sm_33 = DFFE( aa3 $ GND, GLOBAL( clk1), VCC, VCC, VCC);
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information c:\max\shiyan5\jsq\jsq_d.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:01
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 3,387K
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