📄 jsq_d.rpt
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Project Information c:\max\shiyan5\jsq\jsq_d.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 11/05/2007 15:16:56
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
JSQ_D
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
jsq_d EPM7032LC44-6 3 24 0 28 0 87 %
User Pins: 3 24 0
Project Information c:\max\shiyan5\jsq\jsq_d.rpt
** AUTO GLOBAL SIGNALS **
INFO: Signal 'clk1' chosen for auto global Clock
Project Information c:\max\shiyan5\jsq\jsq_d.rpt
** FILE HIERARCHY **
|dffl:u1|
|dffl:u2|
|dffl:u3|
|dffl:u4|
Device-Specific Information: c:\max\shiyan5\jsq\jsq_d.rpt
jsq_d
***** Logic for device 'jsq_d' compiled without errors.
Device: EPM7032LC44-6
Device Options:
Turbo Bit = ON
Security Bit = OFF
s
m c
_ r c V G G G l G
3 s l C N N N k N q q
2 t k C D D D 1 D 3 2
-----------------------------------_
/ 6 5 4 3 2 1 44 43 42 41 40 |
sm_33 | 7 39 | q1
sm_12 | 8 38 | nq2
sm_13 | 9 37 | nq3
GND | 10 36 | q0
sm_22 | 11 35 | VCC
sm_23 | 12 EPM7032LC44-6 34 | nq1
sm3 | 13 33 | nq0
RESERVED | 14 32 | sm_11
VCC | 15 31 | sm_20
sm2 | 16 30 | GND
RESERVED | 17 29 | sm_21
|_ 18 19 20 21 22 23 24 25 26 27 28 _|
------------------------------------
R R R R G V s s s s s
E E E E N C m m m m m
S S S S D C 1 0 _ _ _
E E E E 1 3 3
R R R R 0 1 0
V V V V
E E E E
D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCC = Dedicated power pin, which MUST be connected to VCC.
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
Device-Specific Information: c:\max\shiyan5\jsq\jsq_d.rpt
jsq_d
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 12/16( 75%) 10/16( 62%) 0/16( 0%) 6/36( 16%)
B: LC17 - LC32 16/16(100%) 16/16(100%) 0/16( 0%) 8/36( 22%)
Total dedicated input pins used: 1/4 ( 25%)
Total I/O pins used: 26/32 ( 81%)
Total logic cells used: 28/32 ( 87%)
Total shareable expanders used: 0/32 ( 0%)
Total Turbo logic cells used: 28/32 ( 87%)
Total shareable expanders not available (n/a): 0/32 ( 0%)
Average fan-in: 2.28
Total fan-in: 64
Total input pins required: 3
Total output pins required: 24
Total bidirectional pins required: 0
Total logic cells required: 28
Total flipflops required: 28
Total product terms required: 44
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 0
Synthesized logic cells: 0/ 32 ( 0%)
Device-Specific Information: c:\max\shiyan5\jsq\jsq_d.rpt
jsq_d
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
4 (1) (A) INPUT 0 0 0 0 0 2 0 clk
43 - - INPUT G 0 0 0 0 0 0 0 clk1
5 (2) (A) INPUT 0 0 0 0 0 8 0 rst
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: c:\max\shiyan5\jsq\jsq_d.rpt
jsq_d
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
33 24 B FF t 0 0 0 2 0 3 0 nq0 (|dffl:u1|:7)
34 23 B FF t 0 0 0 1 1 3 0 nq1 (|dffl:u2|:7)
38 20 B FF t 0 0 0 1 1 3 0 nq2 (|dffl:u3|:7)
37 21 B FF t 0 0 0 1 1 1 0 nq3 (|dffl:u4|:7)
36 22 B FF t 0 0 0 2 1 0 1 q0 (|dffl:u1|:6)
39 19 B FF t 0 0 0 1 2 0 1 q1 (|dffl:u2|:6)
40 18 B FF t 0 0 0 1 2 0 1 q2 (|dffl:u3|:6)
41 17 B FF t 0 0 0 1 2 0 1 q3 (|dffl:u4|:6)
25 31 B FF + t 0 0 0 0 1 0 0 sm0
24 32 B FF + t 0 0 0 0 1 0 0 sm1
16 11 A FF + t 0 0 0 0 1 0 0 sm2
13 9 A FF + t 0 0 0 0 1 0 0 sm3
26 30 B FF + t 0 0 0 0 1 0 0 sm_10
32 25 B FF + t 0 0 0 0 1 0 0 sm_11
8 5 A FF + t 0 0 0 0 1 0 0 sm_12
9 6 A FF + t 0 0 0 0 1 0 0 sm_13
31 26 B FF + t 0 0 0 0 1 0 0 sm_20
29 27 B FF + t 0 0 0 0 1 0 0 sm_21
11 7 A FF + t 0 0 0 0 1 0 0 sm_22
12 8 A FF + t 0 0 0 0 1 0 0 sm_23
28 28 B FF + t 0 0 0 0 1 0 0 sm_30
27 29 B FF + t 0 0 0 0 1 0 0 sm_31
6 3 A FF + t 0 0 0 0 1 0 0 sm_32
7 4 A FF + t 0 0 0 0 1 0 0 sm_33
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: c:\max\shiyan5\jsq\jsq_d.rpt
jsq_d
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
(18) 13 A DFFE + t 0 0 0 0 1 4 0 aa3 (:48)
(17) 12 A DFFE + t 0 0 0 0 1 4 0 aa2 (:49)
(14) 10 A DFFE + t 0 0 0 0 1 4 0 aa1 (:50)
(19) 14 A DFFE + t 0 0 0 0 1 4 0 aa0 (:51)
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: c:\max\shiyan5\jsq\jsq_d.rpt
jsq_d
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+----------------------- LC11 sm2
| +--------------------- LC9 sm3
| | +------------------- LC5 sm_12
| | | +----------------- LC6 sm_13
| | | | +--------------- LC7 sm_22
| | | | | +------------- LC8 sm_23
| | | | | | +----------- LC3 sm_32
| | | | | | | +--------- LC4 sm_33
| | | | | | | | +------- LC13 aa3
| | | | | | | | | +----- LC12 aa2
| | | | | | | | | | +--- LC10 aa1
| | | | | | | | | | | +- LC14 aa0
| | | | | | | | | | | |
| | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | that feed LAB 'A'
LC | | | | | | | | | | | | | A B | Logic cells that feed LAB 'A':
LC13 -> - * - * - * - * - - - - | * - | <-- aa3
LC12 -> * - * - * - * - - - - - | * - | <-- aa2
Pin
43 -> - - - - - - - - - - - - | - - | <-- clk1
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