📄 jsq_d.rpt
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14: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\shiyan5\jsq_d.rpt
jsq_d
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 20 clk1
DFF 5 |dffl:u1|nq1
DFF 5 |dffl:u2|nq1
DFF 5 |dffl:u3|nq1
INPUT 2 clk
Device-Specific Information: d:\shiyan5\jsq_d.rpt
jsq_d
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 8 rst
Device-Specific Information: d:\shiyan5\jsq_d.rpt
jsq_d
** EQUATIONS **
clk : INPUT;
clk1 : INPUT;
rst : INPUT;
-- Node name is ':51' = 'aa0'
-- Equation name is 'aa0', location is LC2_B13, type is buried.
aa0 = DFFE( _LC2_B4, GLOBAL( clk1), VCC, VCC, VCC);
-- Node name is ':50' = 'aa1'
-- Equation name is 'aa1', location is LC4_A20, type is buried.
aa1 = DFFE( _LC6_B4, GLOBAL( clk1), VCC, VCC, VCC);
-- Node name is ':49' = 'aa2'
-- Equation name is 'aa2', location is LC1_C4, type is buried.
aa2 = DFFE( _LC1_C12, GLOBAL( clk1), VCC, VCC, VCC);
-- Node name is ':48' = 'aa3'
-- Equation name is 'aa3', location is LC2_C14, type is buried.
aa3 = DFFE( _LC3_C12, GLOBAL( clk1), VCC, VCC, VCC);
-- Node name is 'nq0'
-- Equation name is 'nq0', type is output
nq0 = _LC3_B4;
-- Node name is 'nq1'
-- Equation name is 'nq1', type is output
nq1 = _LC1_B4;
-- Node name is 'nq2'
-- Equation name is 'nq2', type is output
nq2 = _LC6_C12;
-- Node name is 'nq3'
-- Equation name is 'nq3', type is output
nq3 = _LC2_C12;
-- Node name is 'q0'
-- Equation name is 'q0', type is output
q0 = _LC2_B4;
-- Node name is 'q1'
-- Equation name is 'q1', type is output
q1 = _LC6_B4;
-- Node name is 'q2'
-- Equation name is 'q2', type is output
q2 = _LC1_C12;
-- Node name is 'q3'
-- Equation name is 'q3', type is output
q3 = _LC3_C12;
-- Node name is 'sm0'
-- Equation name is 'sm0', type is output
sm0 = _LC7_B13;
-- Node name is 'sm1'
-- Equation name is 'sm1', type is output
sm1 = _LC1_A20;
-- Node name is 'sm2'
-- Equation name is 'sm2', type is output
sm2 = _LC6_C4;
-- Node name is 'sm3'
-- Equation name is 'sm3', type is output
sm3 = _LC6_C14;
-- Node name is 'sm_10'
-- Equation name is 'sm_10', type is output
sm_10 = _LC5_B13;
-- Node name is 'sm_11'
-- Equation name is 'sm_11', type is output
sm_11 = _LC3_A20;
-- Node name is 'sm_12'
-- Equation name is 'sm_12', type is output
sm_12 = _LC2_C4;
-- Node name is 'sm_13'
-- Equation name is 'sm_13', type is output
sm_13 = _LC5_C14;
-- Node name is 'sm_20'
-- Equation name is 'sm_20', type is output
sm_20 = _LC3_B13;
-- Node name is 'sm_21'
-- Equation name is 'sm_21', type is output
sm_21 = _LC2_A20;
-- Node name is 'sm_22'
-- Equation name is 'sm_22', type is output
sm_22 = _LC5_C4;
-- Node name is 'sm_23'
-- Equation name is 'sm_23', type is output
sm_23 = _LC4_C14;
-- Node name is 'sm_30'
-- Equation name is 'sm_30', type is output
sm_30 = _LC1_B13;
-- Node name is 'sm_31'
-- Equation name is 'sm_31', type is output
sm_31 = _LC7_A20;
-- Node name is 'sm_32'
-- Equation name is 'sm_32', type is output
sm_32 = _LC3_C4;
-- Node name is 'sm_33'
-- Equation name is 'sm_33', type is output
sm_33 = _LC1_C14;
-- Node name is '|dffl:u1|:7' = '|dffl:u1|nq1'
-- Equation name is '_LC3_B4', type is buried
!_LC3_B4 = _LC3_B4~NOT;
_LC3_B4~NOT = DFFE( _LC3_B4, GLOBAL( clk), GLOBAL( rst), VCC, VCC);
-- Node name is '|dffl:u1|:6' = '|dffl:u1|q1'
-- Equation name is '_LC2_B4', type is buried
_LC2_B4 = DFFE( _LC3_B4, GLOBAL( clk), GLOBAL( rst), VCC, VCC);
-- Node name is '|dffl:u2|:7' = '|dffl:u2|nq1'
-- Equation name is '_LC1_B4', type is buried
!_LC1_B4 = _LC1_B4~NOT;
_LC1_B4~NOT = DFFE( _LC1_B4, _LC3_B4, GLOBAL( rst), VCC, VCC);
-- Node name is '|dffl:u2|:6' = '|dffl:u2|q1'
-- Equation name is '_LC6_B4', type is buried
_LC6_B4 = DFFE( _LC1_B4, _LC3_B4, GLOBAL( rst), VCC, VCC);
-- Node name is '|dffl:u3|:7' = '|dffl:u3|nq1'
-- Equation name is '_LC6_C12', type is buried
!_LC6_C12 = _LC6_C12~NOT;
_LC6_C12~NOT = DFFE( _LC6_C12, _LC1_B4, GLOBAL( rst), VCC, VCC);
-- Node name is '|dffl:u3|:6' = '|dffl:u3|q1'
-- Equation name is '_LC1_C12', type is buried
_LC1_C12 = DFFE( _LC6_C12, _LC1_B4, GLOBAL( rst), VCC, VCC);
-- Node name is '|dffl:u4|:7' = '|dffl:u4|nq1'
-- Equation name is '_LC2_C12', type is buried
!_LC2_C12 = _LC2_C12~NOT;
_LC2_C12~NOT = DFFE( _LC2_C12, _LC6_C12, GLOBAL( rst), VCC, VCC);
-- Node name is '|dffl:u4|:6' = '|dffl:u4|q1'
-- Equation name is '_LC3_C12', type is buried
_LC3_C12 = DFFE( _LC2_C12, _LC6_C12, GLOBAL( rst), VCC, VCC);
-- Node name is ':12'
-- Equation name is '_LC6_C14', type is buried
_LC6_C14 = DFFE( aa3, GLOBAL( clk1), VCC, VCC, VCC);
-- Node name is ':14'
-- Equation name is '_LC6_C4', type is buried
_LC6_C4 = DFFE( aa2, GLOBAL( clk1), VCC, VCC, VCC);
-- Node name is ':16'
-- Equation name is '_LC1_A20', type is buried
_LC1_A20 = DFFE( aa1, GLOBAL( clk1), VCC, VCC, VCC);
-- Node name is ':18'
-- Equation name is '_LC7_B13', type is buried
_LC7_B13 = DFFE( aa0, GLOBAL( clk1), VCC, VCC, VCC);
-- Node name is ':20'
-- Equation name is '_LC5_C14', type is buried
_LC5_C14 = DFFE( aa3, GLOBAL( clk1), VCC, VCC, VCC);
-- Node name is ':22'
-- Equation name is '_LC2_C4', type is buried
_LC2_C4 = DFFE( aa2, GLOBAL( clk1), VCC, VCC, VCC);
-- Node name is ':24'
-- Equation name is '_LC3_A20', type is buried
_LC3_A20 = DFFE( aa1, GLOBAL( clk1), VCC, VCC, VCC);
-- Node name is ':26'
-- Equation name is '_LC5_B13', type is buried
_LC5_B13 = DFFE( aa0, GLOBAL( clk1), VCC, VCC, VCC);
-- Node name is ':28'
-- Equation name is '_LC4_C14', type is buried
_LC4_C14 = DFFE( aa3, GLOBAL( clk1), VCC, VCC, VCC);
-- Node name is ':30'
-- Equation name is '_LC5_C4', type is buried
_LC5_C4 = DFFE( aa2, GLOBAL( clk1), VCC, VCC, VCC);
-- Node name is ':32'
-- Equation name is '_LC2_A20', type is buried
_LC2_A20 = DFFE( aa1, GLOBAL( clk1), VCC, VCC, VCC);
-- Node name is ':34'
-- Equation name is '_LC3_B13', type is buried
_LC3_B13 = DFFE( aa0, GLOBAL( clk1), VCC, VCC, VCC);
-- Node name is ':36'
-- Equation name is '_LC1_C14', type is buried
_LC1_C14 = DFFE( aa3, GLOBAL( clk1), VCC, VCC, VCC);
-- Node name is ':38'
-- Equation name is '_LC3_C4', type is buried
_LC3_C4 = DFFE( aa2, GLOBAL( clk1), VCC, VCC, VCC);
-- Node name is ':40'
-- Equation name is '_LC7_A20', type is buried
_LC7_A20 = DFFE( aa1, GLOBAL( clk1), VCC, VCC, VCC);
-- Node name is ':42'
-- Equation name is '_LC1_B13', type is buried
_LC1_B13 = DFFE( aa0, GLOBAL( clk1), VCC, VCC, VCC);
Project Information d:\shiyan5\jsq_d.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 10,817K
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