wave.map.eqn

数字示波器的FPGA实现 VHDL编写 Quartus7.1测试通过

W2_q_b[1]_PORT_B_address = BUS(L1_COUNTER[0], L1_COUNTER[1], L1_COUNTER[2], L1_COUNTER[3], L1_COUNTER[4], L1_COUNTER[5], L1_COUNTER[6], L1_COUNTER[7], L1_COUNTER[8], L1_COUNTER[9], L1_COUNTER[10]);
W2_q_b[1]_PORT_B_address_reg = DFFE(W2_q_b[1]_PORT_B_address, W2_q_b[1]_clock_1, , , );
W2_q_b[1]_PORT_A_write_enable = VCC;
W2_q_b[1]_PORT_A_write_enable_reg = DFFE(W2_q_b[1]_PORT_A_write_enable, W2_q_b[1]_clock_0, , , );
W2_q_b[1]_PORT_B_read_enable = VCC;
W2_q_b[1]_PORT_B_read_enable_reg = DFFE(W2_q_b[1]_PORT_B_read_enable, W2_q_b[1]_clock_1, , , );
W2_q_b[1]_clock_0 = CLK;
W2_q_b[1]_clock_1 = CLK;
W2_q_b[1]_PORT_B_data_out = MEMORY(W2_q_b[1]_PORT_A_data_in_reg, , W2_q_b[1]_PORT_A_address_reg, W2_q_b[1]_PORT_B_address_reg, W2_q_b[1]_PORT_A_write_enable_reg, W2_q_b[1]_PORT_B_read_enable_reg, , , W2_q_b[1]_clock_0, W2_q_b[1]_clock_1, , , , );
W2_q_b[1] = W2_q_b[1]_PORT_B_data_out[0];


--G1_RAMTMP5[1] is BUS_1:inst5|RAMTMP5[1]
--operation mode is normal

G1_RAMTMP5[1]_lut_out = A1L84 & (G1L69 # G1_RAMTMP5[1] & Y1_q_a[5]) # !A1L84 & G1_RAMTMP5[1] & Y1_q_a[5];
G1_RAMTMP5[1] = DFFEA(G1_RAMTMP5[1]_lut_out, !CLK, VCC, , G1L92, , );


--W1_q_b[1] is dram:inst|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|q_b[1]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 2048, Port A Width: 1, Port B Depth: 2048, Port B Width: 1
--Port A Logical Depth: 2048, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
W1_q_b[1]_PORT_A_data_in = T1_data[1];
W1_q_b[1]_PORT_A_data_in_reg = DFFE(W1_q_b[1]_PORT_A_data_in, W1_q_b[1]_clock_0, , , );
W1_q_b[1]_PORT_A_address = BUS(T1_cnt2[0], T1_cnt2[1], T1_cnt2[2], T1_cnt2[3], T1_cnt2[4], T1_cnt2[5], T1_cnt2[6], T1_cnt2[7], T1_cnt2[8], T1_cnt2[9], T1_cnt2[10]);
W1_q_b[1]_PORT_A_address_reg = DFFE(W1_q_b[1]_PORT_A_address, W1_q_b[1]_clock_0, , , );
W1_q_b[1]_PORT_B_address = BUS(L1_COUNTER[0], L1_COUNTER[1], L1_COUNTER[2], L1_COUNTER[3], L1_COUNTER[4], L1_COUNTER[5], L1_COUNTER[6], L1_COUNTER[7], L1_COUNTER[8], L1_COUNTER[9], L1_COUNTER[10]);
W1_q_b[1]_PORT_B_address_reg = DFFE(W1_q_b[1]_PORT_B_address, W1_q_b[1]_clock_1, , , );
W1_q_b[1]_PORT_A_write_enable = VCC;
W1_q_b[1]_PORT_A_write_enable_reg = DFFE(W1_q_b[1]_PORT_A_write_enable, W1_q_b[1]_clock_0, , , );
W1_q_b[1]_PORT_B_read_enable = VCC;
W1_q_b[1]_PORT_B_read_enable_reg = DFFE(W1_q_b[1]_PORT_B_read_enable, W1_q_b[1]_clock_1, , , );
W1_q_b[1]_clock_0 = CLK;
W1_q_b[1]_clock_1 = CLK;
W1_q_b[1]_PORT_B_data_out = MEMORY(W1_q_b[1]_PORT_A_data_in_reg, , W1_q_b[1]_PORT_A_address_reg, W1_q_b[1]_PORT_B_address_reg, W1_q_b[1]_PORT_A_write_enable_reg, W1_q_b[1]_PORT_B_read_enable_reg, , , W1_q_b[1]_clock_0, W1_q_b[1]_clock_1, , , , );
W1_q_b[1] = W1_q_b[1]_PORT_B_data_out[0];


--G1_RAMTMP2[1] is BUS_1:inst5|RAMTMP2[1]
--operation mode is normal

G1_RAMTMP2[1]_lut_out = A1L84 & (G1L59 # G1_RAMTMP2[1] & Y1_q_a[6]) # !A1L84 & G1_RAMTMP2[1] & Y1_q_a[6];
G1_RAMTMP2[1] = DFFEA(G1_RAMTMP2[1]_lut_out, !CLK, VCC, , G1L92, , );


--F1L13 is generator_accB:inst4|add~16
--operation mode is arithmetic

F1L13_carry_eqn = F1L03;
F1L13 = F1_REG_Q[15] $ G1_RAMTMP9[7] $ F1L13_carry_eqn;

--F1L23 is generator_accB:inst4|add~16COUT
--operation mode is arithmetic

F1L23 = CARRY(F1_REG_Q[15] & !G1_RAMTMP9[7] & !F1L03 # !F1_REG_Q[15] & (!F1L03 # !G1_RAMTMP9[7]));


--W2_q_b[0] is dram:inst14|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|q_b[0]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 2048, Port A Width: 1, Port B Depth: 2048, Port B Width: 1
--Port A Logical Depth: 2048, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
W2_q_b[0]_PORT_A_data_in = T2_data[0];
W2_q_b[0]_PORT_A_data_in_reg = DFFE(W2_q_b[0]_PORT_A_data_in, W2_q_b[0]_clock_0, , , );
W2_q_b[0]_PORT_A_address = BUS(T2_cnt2[0], T2_cnt2[1], T2_cnt2[2], T2_cnt2[3], T2_cnt2[4], T2_cnt2[5], T2_cnt2[6], T2_cnt2[7], T2_cnt2[8], T2_cnt2[9], T2_cnt2[10]);
W2_q_b[0]_PORT_A_address_reg = DFFE(W2_q_b[0]_PORT_A_address, W2_q_b[0]_clock_0, , , );
W2_q_b[0]_PORT_B_address = BUS(L1_COUNTER[0], L1_COUNTER[1], L1_COUNTER[2], L1_COUNTER[3], L1_COUNTER[4], L1_COUNTER[5], L1_COUNTER[6], L1_COUNTER[7], L1_COUNTER[8], L1_COUNTER[9], L1_COUNTER[10]);
W2_q_b[0]_PORT_B_address_reg = DFFE(W2_q_b[0]_PORT_B_address, W2_q_b[0]_clock_1, , , );
W2_q_b[0]_PORT_A_write_enable = VCC;
W2_q_b[0]_PORT_A_write_enable_reg = DFFE(W2_q_b[0]_PORT_A_write_enable, W2_q_b[0]_clock_0, , , );
W2_q_b[0]_PORT_B_read_enable = VCC;
W2_q_b[0]_PORT_B_read_enable_reg = DFFE(W2_q_b[0]_PORT_B_read_enable, W2_q_b[0]_clock_1, , , );
W2_q_b[0]_clock_0 = CLK;
W2_q_b[0]_clock_1 = CLK;
W2_q_b[0]_PORT_B_data_out = MEMORY(W2_q_b[0]_PORT_A_data_in_reg, , W2_q_b[0]_PORT_A_address_reg, W2_q_b[0]_PORT_B_address_reg, W2_q_b[0]_PORT_A_write_enable_reg, W2_q_b[0]_PORT_B_read_enable_reg, , , W2_q_b[0]_clock_0, W2_q_b[0]_clock_1, , , , );
W2_q_b[0] = W2_q_b[0]_PORT_B_data_out[0];


--G1_RAMTMP5[0] is BUS_1:inst5|RAMTMP5[0]
--operation mode is normal

G1_RAMTMP5[0]_lut_out = A1L94 & (G1L69 # G1_RAMTMP5[0] & Y1_q_a[5]) # !A1L94 & G1_RAMTMP5[0] & Y1_q_a[5];
G1_RAMTMP5[0] = DFFEA(G1_RAMTMP5[0]_lut_out, !CLK, VCC, , G1L92, , );


--W1_q_b[0] is dram:inst|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|q_b[0]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 2048, Port A Width: 1, Port B Depth: 2048, Port B Width: 1
--Port A Logical Depth: 2048, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
W1_q_b[0]_PORT_A_data_in = T1_data[0];
W1_q_b[0]_PORT_A_data_in_reg = DFFE(W1_q_b[0]_PORT_A_data_in, W1_q_b[0]_clock_0, , , );
W1_q_b[0]_PORT_A_address = BUS(T1_cnt2[0], T1_cnt2[1], T1_cnt2[2], T1_cnt2[3], T1_cnt2[4], T1_cnt2[5], T1_cnt2[6], T1_cnt2[7], T1_cnt2[8], T1_cnt2[9], T1_cnt2[10]);
W1_q_b[0]_PORT_A_address_reg = DFFE(W1_q_b[0]_PORT_A_address, W1_q_b[0]_clock_0, , , );
W1_q_b[0]_PORT_B_address = BUS(L1_COUNTER[0], L1_COUNTER[1], L1_COUNTER[2], L1_COUNTER[3], L1_COUNTER[4], L1_COUNTER[5], L1_COUNTER[6], L1_COUNTER[7], L1_COUNTER[8], L1_COUNTER[9], L1_COUNTER[10]);
W1_q_b[0]_PORT_B_address_reg = DFFE(W1_q_b[0]_PORT_B_address, W1_q_b[0]_clock_1, , , );
W1_q_b[0]_PORT_A_write_enable = VCC;
W1_q_b[0]_PORT_A_write_enable_reg = DFFE(W1_q_b[0]_PORT_A_write_enable, W1_q_b[0]_clock_0, , , );
W1_q_b[0]_PORT_B_read_enable = VCC;
W1_q_b[0]_PORT_B_read_enable_reg = DFFE(W1_q_b[0]_PORT_B_read_enable, W1_q_b[0]_clock_1, , , );
W1_q_b[0]_clock_0 = CLK;
W1_q_b[0]_clock_1 = CLK;
W1_q_b[0]_PORT_B_data_out = MEMORY(W1_q_b[0]_PORT_A_data_in_reg, , W1_q_b[0]_PORT_A_address_reg, W1_q_b[0]_PORT_B_address_reg, W1_q_b[0]_PORT_A_write_enable_reg, W1_q_b[0]_PORT_B_read_enable_reg, , , W1_q_b[0]_clock_0, W1_q_b[0]_clock_1, , , , );
W1_q_b[0] = W1_q_b[0]_PORT_B_data_out[0];


--G1_RAMTMP2[0] is BUS_1:inst5|RAMTMP2[0]
--operation mode is normal

G1_RAMTMP2[0]_lut_out = A1L94 & (G1L59 # G1_RAMTMP2[0] & Y1_q_a[6]) # !A1L94 & G1_RAMTMP2[0] & Y1_q_a[6];
G1_RAMTMP2[0] = DFFEA(G1_RAMTMP2[0]_lut_out, !CLK, VCC, , G1L92, , );


--F1L92 is generator_accB:inst4|add~15
--operation mode is arithmetic

F1L92_carry_eqn = F1L82;
F1L92 = F1_REG_Q[14] $ G1_RAMTMP9[6] $ !F1L92_carry_eqn;

--F1L03 is generator_accB:inst4|add~15COUT
--operation mode is arithmetic

F1L03 = CARRY(F1_REG_Q[14] & (G1_RAMTMP9[6] # !F1L82) # !F1_REG_Q[14] & G1_RAMTMP9[6] & !F1L82);


--F1L72 is generator_accB:inst4|add~14
--operation mode is arithmetic

F1L72_carry_eqn = F1L62;
F1L72 = F1_REG_Q[13] $ G1_RAMTMP9[5] $ F1L72_carry_eqn;

--F1L82 is generator_accB:inst4|add~14COUT
--operation mode is arithmetic

F1L82 = CARRY(F1_REG_Q[13] & !G1_RAMTMP9[5] & !F1L62 # !F1_REG_Q[13] & (!F1L62 # !G1_RAMTMP9[5]));


--F1L52 is generator_accB:inst4|add~13
--operation mode is arithmetic

F1L52_carry_eqn = F1L42;
F1L52 = F1_REG_Q[12] $ G1_RAMTMP9[4] $ !F1L52_carry_eqn;

--F1L62 is generator_accB:inst4|add~13COUT
--operation mode is arithmetic

F1L62 = CARRY(F1_REG_Q[12] & (G1_RAMTMP9[4] # !F1L42) # !F1_REG_Q[12] & G1_RAMTMP9[4] & !F1L42);


--H1_TEMP[15] is FREQ_COUNT:inst6|TEMP[15]
--operation mode is normal

H1_TEMP[15]_lut_out = AB1_safe_q[15];
H1_TEMP[15] = DFFEA(H1_TEMP[15]_lut_out, CLK2, VCC, , H1L04, , );


--D1_Q[7] is AMPL_COUNT:inst2|Q[7]
--operation mode is normal

D1_Q[7]_carry_eqn = D1L49;
D1_Q[7]_lut_out = D1_MIN[7] $ D1_MAX[7] $ D1_Q[7]_carry_eqn;
D1_Q[7] = DFFEA(D1_Q[7]_lut_out, P1_CLK, VCC, , D1L18, , );


--G1L39 is BUS_1:inst5|reduce_nor~2
--operation mode is normal

G1L39 = G1_LATCH_ADDRES[0] # G1_LATCH_ADDRES[3] # !G1L001;


--G1L02 is BUS_1:inst5|P0_OUT~1200
--operation mode is normal

G1L02 = G1_P0_OUT[7] & (D1_Q[7] # G1L39) # !G1_P0_OUT[7] & D1_Q[7] & !G1L39;


--H1_TEMP[7] is FREQ_COUNT:inst6|TEMP[7]
--operation mode is normal

H1_TEMP[7]_lut_out = AB1_safe_q[7];
H1_TEMP[7] = DFFEA(H1_TEMP[7]_lut_out, CLK2, VCC, , H1L04, , );


--G1L201 is BUS_1:inst5|reduce_nor~173
--operation mode is normal

G1L201 = G1L99 & !G1_LATCH_ADDRES[3] & !G1_LATCH_ADDRES[1];


--G1L29 is BUS_1:inst5|reduce_nor~1
--operation mode is normal

G1L29 = G1_LATCH_ADDRES[2] # !G1L201 # !G1_LATCH_ADDRES[0];


--G1L19 is BUS_1:inst5|reduce_nor~0
--operation mode is normal

G1L19 = !G1_LATCH_ADDRES[0] & !G1_LATCH_ADDRES[2] & G1L201;


--G1L82 is BUS_1:inst5|process1~0
--operation mode is normal

G1L82 = !CS & !RD;


--H1_TEMP[14] is FREQ_COUNT:inst6|TEMP[14]
--operation mode is normal

H1_TEMP[14]_lut_out = AB1_safe_q[14];
H1_TEMP[14] = DFFEA(H1_TEMP[14]_lut_out, CLK2, VCC, , H1L04, , );


--D1_Q[6] is AMPL_COUNT:inst2|Q[6]
--operation mode is arithmetic

D1_Q[6]_carry_eqn = D1L29;
D1_Q[6]_lut_out = D1_MIN[6] $ D1_MAX[6] $ !D1_Q[6]_carry_eqn;
D1_Q[6] = DFFEA(D1_Q[6]_lut_out, P1_CLK, VCC, , D1L18, , );

--D1L49 is AMPL_COUNT:inst2|Q[6]~COUT
--operation mode is arithmetic

D1L49 = CARRY(D1_MIN[6] & (D1_MAX[6] # !D1L29) # !D1_MIN[6] & D1_MAX[6] & !D1L29);


--G1L12 is BUS_1:inst5|P0_OUT~1201
--operation mode is normal

G1L12 = G1_P0_OUT[6] & (D1_Q[6] # G1L39) # !G1_P0_OUT[6] & D1_Q[6] & !G1L39;


--H1_TEMP[6] is FREQ_COUNT:inst6|TEMP[6]
--operation mode is normal

H1_TEMP[6]_lut_out = AB1_safe_q[6];
H1_TEMP[6] = DFFEA(H1_TEMP[6]_lut_out, CLK2, VCC, , H1L04, , );


--H1_TEMP[13] is FREQ_COUNT:inst6|TEMP[13]
--operation mode is normal

H1_TEMP[13]_lut_out = AB1_safe_q[13];
H1_TEMP[13] = DFFEA(H1_TEMP[13]_lut_out, CLK2, VCC, , H1L04, , );


--D1_Q[5] is AMPL_COUNT:inst2|Q[5]
--operation mode is arithmetic

D1_Q[5]_carry_eqn = D1L09;
D1_Q[5]_lut_out = D1_MIN[5] $ D1_MAX[5] $ D1_Q[5]_carry_eqn;
D1_Q[5] = DFFEA(D1_Q[5]_lut_out, P1_CLK, VCC, , D1L18, , );

--D1L29 is AMPL_COUNT:inst2|Q[5]~COUT
--operation mode is arithmetic

D1L29 = CARRY(D1_MIN[5] & !D1_MAX[5] & !D1L09 # !D1_MIN[5] & (!D1L09 # !D1_MAX[5]));


--G1L22 is BUS_1:inst5|P0_OUT~1202
--operation mode is normal

G1L22 = G1_P0_OUT[5] & (D1_Q[5] # G1L39) # !G1_P0_OUT[5] & D1_Q[5] & !G1L39;


--H1_TEMP[5] is FREQ_COUNT:inst6|TEMP[5]
--operation mode is normal

H1_TEMP[5]_lut_out = AB1_safe_q[5];
H1_TEMP[5] = DFFEA(H1_TEMP[5]_lut_out, CLK2, VCC, , H1L04, , );


--H1_TEMP[12] is FREQ_COUNT:inst6|TEMP[12]
--operation mode is normal

H1_TEMP[12]_lut_out = AB1_safe_q[12];
H1_TEMP[12] = DFFEA(H1_TEMP[12]_lut_out, CLK2, VCC, , H1L04, , );


--D1_Q[4] is AMPL_COUNT:inst2|Q[4]
--operation mode is arithmetic

D1_Q[4]_carry_eqn = D1L88;
D1_Q[4]_lut_out = D1_MIN[4] $ D1_MAX[4] $ !D1_Q[4]_carry_eqn;
D1_Q[4] = DFFEA(D1_Q[4]_lut_out, P1_CLK, VCC, , D1L18, , );

--D1L09 is AMPL_COUNT:inst2|Q[4]~COUT
--operation mode is arithmetic

D1L09 = CARRY(D1_MIN[4] & (D1_MAX[4] # !D1L88) # !D1_MIN[4] & D1_MAX[4] & !D1L88);


--G1L32 is BUS_1:inst5|P0_OUT~1203
--operation mode is normal

G1L32 = G1_P0_OUT[4] & (D1_Q[4] # G1L39) # !G1_P0_OUT[4] & D1_Q[4] & !G1L39;


--H1_TEMP[4] is FREQ_COUNT:inst6|TEMP[4]
--operation mode is normal

H1_TEMP[4]_lut_out = AB1_safe_q[4];
H1_TEMP[4] = DFFEA(H1_TEMP[4]_lut_out, CLK2, VCC, , H1L04, , );


--H1_TEMP[11] is FREQ_COUNT:inst6|TEMP[11]
--operation mode is normal

H1_TEMP[11]_lut_out = AB1_safe_q[11];
H1_TEMP[11] = DFFEA(H1_TEMP[11]_lut_out, CLK2, VCC, , H1L04, , );


--D1_Q[3] is AMPL_COUNT:inst2|Q[3]
--operation mode is arithmetic

D1_Q[3]_carry_eqn = D1L68;
D1_Q[3]_lut_out = D1_MIN[3] $ D1_MAX[3] $ D1_Q[3]_carry_eqn;
D1_Q[3] = DFFEA(D1_Q[3]_lut_out, P1_CLK, VCC, , D1L18, , );

--D1L88 is AMPL_COUNT:inst2|Q[3]~COUT
--operation mode is arithmetic

D1L88 = CARRY(D1_MIN[3] & !D1_MAX[3] & !D1L68 # !D1_MIN[3] & (!D1L68 # !D1_MAX[3]));


--G1L42 is BUS_1:inst5|P0_OUT~1204
--operation mode is normal

G1L42 = G1_P0_OUT[3] & (D1_Q[3] # G1L39) # !G1_P0_OU