wave.map.eqn

数字示波器的FPGA实现 VHDL编写 Quartus7.1测试通过

--G1_RAMTMP2[7] is BUS_1:inst5|RAMTMP2[7]
--operation mode is normal

G1_RAMTMP2[7]_lut_out = A1L24 & (G1L59 # G1_RAMTMP2[7] & Y1_q_a[6]) # !A1L24 & G1_RAMTMP2[7] & Y1_q_a[6];
G1_RAMTMP2[7] = DFFEA(G1_RAMTMP2[7]_lut_out, !CLK, VCC, , G1L92, , );


--N2L82 is VOLTAGE_CONV:inst15|LessThan~7
--operation mode is arithmetic

N2L82 = CARRY(N2L31 & W1_q_b[6] & !N2L62 # !N2L31 & (W1_q_b[6] # !N2L62));


--G1L101 is BUS_1:inst5|reduce_nor~172
--operation mode is normal

G1L101 = G1_LATCH_ADDRES[0] & G1_LATCH_ADDRES[3] & G1L99 & G1_LATCH_ADDRES[2];


--Y1_q_a[3] is BUS_1:inst5|altsyncram:reduce_or_rtl_1|altsyncram_7vi:auto_generated|q_a[3]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
Y1_q_a[3]_PORT_A_address = BUS(A1L34, A1L44, A1L54, A1L64, A1L74, A1L84, A1L94, A1L24);
Y1_q_a[3]_PORT_A_address_reg = DFFE(Y1_q_a[3]_PORT_A_address, Y1_q_a[3]_clock_0, , , );
Y1_q_a[3]_clock_0 = !ALE;
Y1_q_a[3]_PORT_A_data_out = MEMORY(, , Y1_q_a[3]_PORT_A_address_reg, , , , , , Y1_q_a[3]_clock_0, , , , , );
Y1_q_a[3] = Y1_q_a[3]_PORT_A_data_out[0];


--F1L33 is generator_accB:inst4|add~17
--operation mode is arithmetic

F1L33_carry_eqn = F1L23;
F1L33 = F1_REG_Q[16] $ !F1L33_carry_eqn;

--F1L43 is generator_accB:inst4|add~17COUT
--operation mode is arithmetic

F1L43 = CARRY(F1_REG_Q[16] & !F1L23);


--W2_q_b[6] is dram:inst14|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|q_b[6]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 2048, Port A Width: 1, Port B Depth: 2048, Port B Width: 1
--Port A Logical Depth: 2048, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
W2_q_b[6]_PORT_A_data_in = T2_data[6];
W2_q_b[6]_PORT_A_data_in_reg = DFFE(W2_q_b[6]_PORT_A_data_in, W2_q_b[6]_clock_0, , , );
W2_q_b[6]_PORT_A_address = BUS(T2_cnt2[0], T2_cnt2[1], T2_cnt2[2], T2_cnt2[3], T2_cnt2[4], T2_cnt2[5], T2_cnt2[6], T2_cnt2[7], T2_cnt2[8], T2_cnt2[9], T2_cnt2[10]);
W2_q_b[6]_PORT_A_address_reg = DFFE(W2_q_b[6]_PORT_A_address, W2_q_b[6]_clock_0, , , );
W2_q_b[6]_PORT_B_address = BUS(L1_COUNTER[0], L1_COUNTER[1], L1_COUNTER[2], L1_COUNTER[3], L1_COUNTER[4], L1_COUNTER[5], L1_COUNTER[6], L1_COUNTER[7], L1_COUNTER[8], L1_COUNTER[9], L1_COUNTER[10]);
W2_q_b[6]_PORT_B_address_reg = DFFE(W2_q_b[6]_PORT_B_address, W2_q_b[6]_clock_1, , , );
W2_q_b[6]_PORT_A_write_enable = VCC;
W2_q_b[6]_PORT_A_write_enable_reg = DFFE(W2_q_b[6]_PORT_A_write_enable, W2_q_b[6]_clock_0, , , );
W2_q_b[6]_PORT_B_read_enable = VCC;
W2_q_b[6]_PORT_B_read_enable_reg = DFFE(W2_q_b[6]_PORT_B_read_enable, W2_q_b[6]_clock_1, , , );
W2_q_b[6]_clock_0 = CLK;
W2_q_b[6]_clock_1 = CLK;
W2_q_b[6]_PORT_B_data_out = MEMORY(W2_q_b[6]_PORT_A_data_in_reg, , W2_q_b[6]_PORT_A_address_reg, W2_q_b[6]_PORT_B_address_reg, W2_q_b[6]_PORT_A_write_enable_reg, W2_q_b[6]_PORT_B_read_enable_reg, , , W2_q_b[6]_clock_0, W2_q_b[6]_clock_1, , , , );
W2_q_b[6] = W2_q_b[6]_PORT_B_data_out[0];


--G1_RAMTMP5[6] is BUS_1:inst5|RAMTMP5[6]
--operation mode is normal

G1_RAMTMP5[6]_lut_out = A1L34 & (G1L69 # G1_RAMTMP5[6] & Y1_q_a[5]) # !A1L34 & G1_RAMTMP5[6] & Y1_q_a[5];
G1_RAMTMP5[6] = DFFEA(G1_RAMTMP5[6]_lut_out, !CLK, VCC, , G1L92, , );


--W1_q_b[6] is dram:inst|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|q_b[6]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 2048, Port A Width: 1, Port B Depth: 2048, Port B Width: 1
--Port A Logical Depth: 2048, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
W1_q_b[6]_PORT_A_data_in = T1_data[6];
W1_q_b[6]_PORT_A_data_in_reg = DFFE(W1_q_b[6]_PORT_A_data_in, W1_q_b[6]_clock_0, , , );
W1_q_b[6]_PORT_A_address = BUS(T1_cnt2[0], T1_cnt2[1], T1_cnt2[2], T1_cnt2[3], T1_cnt2[4], T1_cnt2[5], T1_cnt2[6], T1_cnt2[7], T1_cnt2[8], T1_cnt2[9], T1_cnt2[10]);
W1_q_b[6]_PORT_A_address_reg = DFFE(W1_q_b[6]_PORT_A_address, W1_q_b[6]_clock_0, , , );
W1_q_b[6]_PORT_B_address = BUS(L1_COUNTER[0], L1_COUNTER[1], L1_COUNTER[2], L1_COUNTER[3], L1_COUNTER[4], L1_COUNTER[5], L1_COUNTER[6], L1_COUNTER[7], L1_COUNTER[8], L1_COUNTER[9], L1_COUNTER[10]);
W1_q_b[6]_PORT_B_address_reg = DFFE(W1_q_b[6]_PORT_B_address, W1_q_b[6]_clock_1, , , );
W1_q_b[6]_PORT_A_write_enable = VCC;
W1_q_b[6]_PORT_A_write_enable_reg = DFFE(W1_q_b[6]_PORT_A_write_enable, W1_q_b[6]_clock_0, , , );
W1_q_b[6]_PORT_B_read_enable = VCC;
W1_q_b[6]_PORT_B_read_enable_reg = DFFE(W1_q_b[6]_PORT_B_read_enable, W1_q_b[6]_clock_1, , , );
W1_q_b[6]_clock_0 = CLK;
W1_q_b[6]_clock_1 = CLK;
W1_q_b[6]_PORT_B_data_out = MEMORY(W1_q_b[6]_PORT_A_data_in_reg, , W1_q_b[6]_PORT_A_address_reg, W1_q_b[6]_PORT_B_address_reg, W1_q_b[6]_PORT_A_write_enable_reg, W1_q_b[6]_PORT_B_read_enable_reg, , , W1_q_b[6]_clock_0, W1_q_b[6]_clock_1, , , , );
W1_q_b[6] = W1_q_b[6]_PORT_B_data_out[0];


--G1_RAMTMP2[6] is BUS_1:inst5|RAMTMP2[6]
--operation mode is normal

G1_RAMTMP2[6]_lut_out = A1L34 & (G1L59 # G1_RAMTMP2[6] & Y1_q_a[6]) # !A1L34 & G1_RAMTMP2[6] & Y1_q_a[6];
G1_RAMTMP2[6] = DFFEA(G1_RAMTMP2[6]_lut_out, !CLK, VCC, , G1L92, , );


--W2_q_b[5] is dram:inst14|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|q_b[5]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 2048, Port A Width: 1, Port B Depth: 2048, Port B Width: 1
--Port A Logical Depth: 2048, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
W2_q_b[5]_PORT_A_data_in = T2_data[5];
W2_q_b[5]_PORT_A_data_in_reg = DFFE(W2_q_b[5]_PORT_A_data_in, W2_q_b[5]_clock_0, , , );
W2_q_b[5]_PORT_A_address = BUS(T2_cnt2[0], T2_cnt2[1], T2_cnt2[2], T2_cnt2[3], T2_cnt2[4], T2_cnt2[5], T2_cnt2[6], T2_cnt2[7], T2_cnt2[8], T2_cnt2[9], T2_cnt2[10]);
W2_q_b[5]_PORT_A_address_reg = DFFE(W2_q_b[5]_PORT_A_address, W2_q_b[5]_clock_0, , , );
W2_q_b[5]_PORT_B_address = BUS(L1_COUNTER[0], L1_COUNTER[1], L1_COUNTER[2], L1_COUNTER[3], L1_COUNTER[4], L1_COUNTER[5], L1_COUNTER[6], L1_COUNTER[7], L1_COUNTER[8], L1_COUNTER[9], L1_COUNTER[10]);
W2_q_b[5]_PORT_B_address_reg = DFFE(W2_q_b[5]_PORT_B_address, W2_q_b[5]_clock_1, , , );
W2_q_b[5]_PORT_A_write_enable = VCC;
W2_q_b[5]_PORT_A_write_enable_reg = DFFE(W2_q_b[5]_PORT_A_write_enable, W2_q_b[5]_clock_0, , , );
W2_q_b[5]_PORT_B_read_enable = VCC;
W2_q_b[5]_PORT_B_read_enable_reg = DFFE(W2_q_b[5]_PORT_B_read_enable, W2_q_b[5]_clock_1, , , );
W2_q_b[5]_clock_0 = CLK;
W2_q_b[5]_clock_1 = CLK;
W2_q_b[5]_PORT_B_data_out = MEMORY(W2_q_b[5]_PORT_A_data_in_reg, , W2_q_b[5]_PORT_A_address_reg, W2_q_b[5]_PORT_B_address_reg, W2_q_b[5]_PORT_A_write_enable_reg, W2_q_b[5]_PORT_B_read_enable_reg, , , W2_q_b[5]_clock_0, W2_q_b[5]_clock_1, , , , );
W2_q_b[5] = W2_q_b[5]_PORT_B_data_out[0];


--G1_RAMTMP5[5] is BUS_1:inst5|RAMTMP5[5]
--operation mode is normal

G1_RAMTMP5[5]_lut_out = A1L44 & (G1L69 # G1_RAMTMP5[5] & Y1_q_a[5]) # !A1L44 & G1_RAMTMP5[5] & Y1_q_a[5];
G1_RAMTMP5[5] = DFFEA(G1_RAMTMP5[5]_lut_out, !CLK, VCC, , G1L92, , );


--W1_q_b[5] is dram:inst|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|q_b[5]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 2048, Port A Width: 1, Port B Depth: 2048, Port B Width: 1
--Port A Logical Depth: 2048, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
W1_q_b[5]_PORT_A_data_in = T1_data[5];
W1_q_b[5]_PORT_A_data_in_reg = DFFE(W1_q_b[5]_PORT_A_data_in, W1_q_b[5]_clock_0, , , );
W1_q_b[5]_PORT_A_address = BUS(T1_cnt2[0], T1_cnt2[1], T1_cnt2[2], T1_cnt2[3], T1_cnt2[4], T1_cnt2[5], T1_cnt2[6], T1_cnt2[7], T1_cnt2[8], T1_cnt2[9], T1_cnt2[10]);
W1_q_b[5]_PORT_A_address_reg = DFFE(W1_q_b[5]_PORT_A_address, W1_q_b[5]_clock_0, , , );
W1_q_b[5]_PORT_B_address = BUS(L1_COUNTER[0], L1_COUNTER[1], L1_COUNTER[2], L1_COUNTER[3], L1_COUNTER[4], L1_COUNTER[5], L1_COUNTER[6], L1_COUNTER[7], L1_COUNTER[8], L1_COUNTER[9], L1_COUNTER[10]);
W1_q_b[5]_PORT_B_address_reg = DFFE(W1_q_b[5]_PORT_B_address, W1_q_b[5]_clock_1, , , );
W1_q_b[5]_PORT_A_write_enable = VCC;
W1_q_b[5]_PORT_A_write_enable_reg = DFFE(W1_q_b[5]_PORT_A_write_enable, W1_q_b[5]_clock_0, , , );
W1_q_b[5]_PORT_B_read_enable = VCC;
W1_q_b[5]_PORT_B_read_enable_reg = DFFE(W1_q_b[5]_PORT_B_read_enable, W1_q_b[5]_clock_1, , , );
W1_q_b[5]_clock_0 = CLK;
W1_q_b[5]_clock_1 = CLK;
W1_q_b[5]_PORT_B_data_out = MEMORY(W1_q_b[5]_PORT_A_data_in_reg, , W1_q_b[5]_PORT_A_address_reg, W1_q_b[5]_PORT_B_address_reg, W1_q_b[5]_PORT_A_write_enable_reg, W1_q_b[5]_PORT_B_read_enable_reg, , , W1_q_b[5]_clock_0, W1_q_b[5]_clock_1, , , , );
W1_q_b[5] = W1_q_b[5]_PORT_B_data_out[0];


--G1_RAMTMP2[5] is BUS_1:inst5|RAMTMP2[5]
--operation mode is normal

G1_RAMTMP2[5]_lut_out = A1L44 & (G1L59 # G1_RAMTMP2[5] & Y1_q_a[6]) # !A1L44 & G1_RAMTMP2[5] & Y1_q_a[6];
G1_RAMTMP2[5] = DFFEA(G1_RAMTMP2[5]_lut_out, !CLK, VCC, , G1L92, , );


--W2_q_b[4] is dram:inst14|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|q_b[4]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 2048, Port A Width: 1, Port B Depth: 2048, Port B Width: 1
--Port A Logical Depth: 2048, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
W2_q_b[4]_PORT_A_data_in = T2_data[4];
W2_q_b[4]_PORT_A_data_in_reg = DFFE(W2_q_b[4]_PORT_A_data_in, W2_q_b[4]_clock_0, , , );
W2_q_b[4]_PORT_A_address = BUS(T2_cnt2[0], T2_cnt2[1], T2_cnt2[2], T2_cnt2[3], T2_cnt2[4], T2_cnt2[5], T2_cnt2[6], T2_cnt2[7], T2_cnt2[8], T2_cnt2[9], T2_cnt2[10]);
W2_q_b[4]_PORT_A_address_reg = DFFE(W2_q_b[4]_PORT_A_address, W2_q_b[4]_clock_0, , , );
W2_q_b[4]_PORT_B_address = BUS(L1_COUNTER[0], L1_COUNTER[1], L1_COUNTER[2], L1_COUNTER[3], L1_COUNTER[4], L1_COUNTER[5], L1_COUNTER[6], L1_COUNTER[7], L1_COUNTER[8], L1_COUNTER[9], L1_COUNTER[10]);
W2_q_b[4]_PORT_B_address_reg = DFFE(W2_q_b[4]_PORT_B_address, W2_q_b[4]_clock_1, , , );
W2_q_b[4]_PORT_A_write_enable = VCC;
W2_q_b[4]_PORT_A_write_enable_reg = DFFE(W2_q_b[4]_PORT_A_write_enable, W2_q_b[4]_clock_0, , , );
W2_q_b[4]_PORT_B_read_enable = VCC;
W2_q_b[4]_PORT_B_read_enable_reg = DFFE(W2_q_b[4]_PORT_B_read_enable, W2_q_b[4]_clock_1, , , );
W2_q_b[4]_clock_0 = CLK;
W2_q_b[4]_clock_1 = CLK;
W2_q_b[4]_PORT_B_data_out = MEMORY(W2_q_b[4]_PORT_A_data_in_reg, , W2_q_b[4]_PORT_A_address_reg, W2_q_b[4]_PORT_B_address_reg, W2_q_b[4]_PORT_A_write_enable_reg, W2_q_b[4]_PORT_B_read_enable_reg, , , W2_q_b[4]_clock_0, W2_q_b[4]_clock_1, , , , );
W2_q_b[4] = W2_q_b[4]_PORT_B_data_out[0];


--G1_RAMTMP5[4] is BUS_1:inst5|RAMTMP5[4]
--operation mode is normal

G1_RAMTMP5[4]_lut_out = A1L54 & (G1L69 # G1_RAMTMP5[4] & Y1_q_a[5]) # !A1L54 & G1_RAMTMP5[4] & Y1_q_a[5];
G1_RAMTMP5[4] = DFFEA(G1_RAMTMP5[4]_lut_out, !CLK, VCC, , G1L92, , );


--W1_q_b[4] is dram:inst|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|q_b[4]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 2048, Port A Width: 1, Port B Depth: 2048, Port B Width: 1
--Port A Logical Depth: 2048, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
W1_q_b[4]_PORT_A_data_in = T1_data[4];
W1_q_b[4]_PORT_A_data_in_reg = DFFE(W1_q_b[4]_PORT_A_data_in, W1_q_b[4]_clock_0, , , );
W1_q_b[4]_PORT_A_address = BUS(T1_cnt2[0], T1_cnt2[1], T1_cnt2[2], T1_cnt2[3], T1_cnt2[4], T1_cnt2[5], T1_cnt2[6], T1_cnt2[7], T1_cnt2[8], T1_cnt2[9], T1_cnt2[10]);
W1_q_b[4]_PORT_A_address_reg = DFFE(W1_q_b[4]_PORT_A_address, W1_q_b[4]_clock_0, , , );
W1_q_b[4]_PORT_B_address = BUS(L1_COUNTER[0], L1_COUNTER[1], L1_COUNTER[2], L1_COUNTER[3], L1_COUNTER[4], L1_COUNTER[5], L1_COUNTER[6], L1_COUNTER[7], L1_COUNTER[8], L1_COUNTER[9], L1_COUNTER[10]);
W1_q_b[4]_PORT_B_address_reg = DFFE(W1_q_b[4]_PORT_B_address, W1_q_b[4]_clock_1, , , );
W1_q_b[4]_PORT_A_write_enable = VCC;
W1_q_b[4]_PORT_A_write_enable_reg = DFFE(W1_q_b[4]_PORT_A_write_enable, W1_q_b[4]_clock_0, , , );
W1_q_b[4]_PORT_B_read_enable = VCC;
W1_q_b[4]_PORT_B_read_enable_reg = DFFE(W1_q_b[4]_PORT_B_read_enable, W1_q_b[4]_clock_1, , , );
W1_q_b[4]_clock_0 = CLK;
W1_q_b[4]_clock_1 = CLK;
W1_q_b[4]_PORT_B_data_out = MEMORY(W1_q_b[4]_PORT_A_data_in_reg, , W1_q_b[4]_PORT_A_address_reg, W1_q_b[4]_PORT_B_address_reg, W1_q_b[4]_PORT_A_write_enable_reg, W1_q_b[4]_PORT_B_read_enable_reg, , , W1_q_b[4]_clock_0, W1_q_b[4]_clock_1, , , , );
W1_q_b[4] = W1_q_b[4]_PORT_B_data_out[0];


--G1_RAMTMP2[4] is BUS_1:inst5|RAMTMP2[4]
--operation mode is normal

G1_RAMTMP2[4]_lut_out = A1L54 & (G1L59 # G1_RAMTMP2[4] & Y1_q_a[6]) # !A1L54 & G1_RAMTMP2[4] & Y1_q_a[6];
G1_RAMTMP2[4] = DFFEA(G1_RAMTMP2[4]_lut_out, !CLK, VCC, , G1L92, , );


--W2_q_b[3] is dram:inst14|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|q_b[3]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 2048, Port A Width: 1, Port B Depth: 2048, Port B Width: 1
--Port A Logical Depth: 2048, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
W2_q_b[3]_PORT_A_data_in = T2_data[3];
W2_q_b[3]_PORT_A_data_in_reg = DFFE(W2_q_b[3]_PORT_A_data_in, W2_q_b[3]_clock_0, , , );
W2_q_b[3]_PORT_A_address = BUS(T2_cnt2[0], T2_cnt2[1], T2_cnt2[2], T2_cnt2[3], T2_cnt2[4], T2_cnt2[5], T2_cnt2[6], T2_cnt2[7], T2_cnt2[8], T2_cnt2[9], T2_cnt2[10]);
W2_q_b[3]_PORT_A_address_reg = DFFE(W2_q_b[3]_PORT_A_address, W2_q_b[3]_clock_0, , , );
W2_q_b[3]_PORT_B_address = BUS(L1_COUNTER[0], L1_COUNTER[1], L1_COUNTER[2], L1_COUNTER[3], L1_COUNTER[4], L1_COUNTER[5], L1_COUNTER[6], L1_COUNTER[7], L1_COUNTER[8], L1_COUNTER[9], L1_COUNTER[10]);
W2_q_b[3]_PORT_B_address_reg = DFFE(W2_q_b[3]_PORT_B_address, W2_q_b[3]_clock_1, , , );
W2_q_b[3]_PORT_A_write_enable = VCC;
W2_q_b[3]_PORT_A_write_enable_reg = DFFE(W2_q_b[3]_PORT_A_write_enable, W2_q_b[3]_clock_0, , , );
W2_q_b[3]_PORT_B_read_enable = VCC;
W2_q_b[3]_PORT_B_read_enable_reg = DFFE(W2_q_b[3]_PORT_B_read_enable, W2_q_b[3]_clock_1, , , );
W2_q_b[3]_clock_0 = CLK;
W2_q_b[3]_clock_1 = CLK;
W2_q_b[3]_PORT_B_data_out = MEMORY(W2_q_b[3]_PORT_A_data_in_reg, , W2_q_b[3]_PORT_A_address_reg, W2_q_b[3]_PORT_B_address_reg, W2_q_b[3]_PORT_A_write_enable_reg, W2_q_b[3]_PORT_B_read_enable_reg, , , W2_q_b[3]_clock_0, W2_q_b[3]_clock_1, , , , );
W2_q_b[3] = W2_q_b[3]_PORT_B_data_out[0];


--G1_RAMTMP5[3] is BUS_1:inst5|RAMTMP5[3]
--operation mode is normal

G1_RAMTMP5[3]_lut_out = A1L64 & (G1L69 # G1_RAMTMP5[3] & Y1_q_a[5]) # !A1L64 & G1_RAMTMP5[3] & Y1_q_a[5];
G1_RAMTMP5[3] = DFFEA(G1_RAMTMP5[3]_lut_out, !CLK, VCC, , G1L92, , );


--W1_q_b[3] is dram:inst|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|q_b[3]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 2048, Port A Width: 1, Port B Depth: 2048, Port B Width: 1
--Port A Logical Depth: 2048, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
W1_q_b[3]_PORT_A_data_in = T1_data[3];
W1_q_b[3]_PORT_A_data_in_reg = DFFE(W1_q_b[3]_PORT_A_data_in, W1_q_b[3]_clock_0, , , );
W1_q_b[3]_PORT_A_address = BUS(T1_cnt2[0], T1_cnt2[1], T1_cnt2[2], T1_cnt2[3], T1_cnt2[4], T1_cnt2[5], T1_cnt2[6], T1_cnt2[7], T1_cnt2[8], T1_cnt2[9], T1_cnt2[10]);
W1_q_b[3]_PORT_A_address_reg = DFFE(W1_q_b[3]_PORT_A_address, W1_q_b[3]_clock_0, , , );
W1_q_b[3]_PORT_B_address = BUS(L1_COUNTER[0], L1_COUNTER[1], L1_COUNTER[2], L1_COUNTER[3], L1_COUNTER[4], L1_COUNTER[5], L1_COUNTER[6], L1_COUNTER[7], L1_COUNTER[8], L1_COUNTER[9], L1_COUNTER[10]);
W1_q_b[3]_PORT_B_address_reg = DFFE(W1_q_b[3]_PORT_B_address, W1_q_b[3]_clock_1, , , );
W1_q_b[3]_PORT_A_write_enable = VCC;
W1_q_b[3]_PORT_A_write_enable_reg = DFFE(W1_q_b[3]_PORT_A_write_enable, W1_q_b[3]_clock_0, , , );
W1_q_b[3]_PORT_B_read_enable = VCC;
W1_q_b[3]_PORT_B_read_enable_reg = DFFE(W1_q_b[3]_PORT_B_read_enable, W1_q_b[3]_clock_1, , , );
W1_q_b[3]_clock_0 = CLK;
W1_q_b[3]_clock_1 = CLK;
W1_q_b[3]_PORT_B_data_out = MEMORY(W1_q_b[3]_PORT_A_data_in_reg, , W1_q_b[3]_PORT_A_address_reg, W1_q_b[3]_PORT_B_address_reg, W1_q_b[3]_PORT_A_write_enable_reg, W1_q_b[3]_PORT_B_read_enable_reg, , , W1_q_b[3]_clock_0, W1_q_b[3]_clock_1, , , , );
W1_q_b[3] = W1_q_b[3]_PORT_B_data_out[0];


--G1_RAMTMP2[3] is BUS_1:inst5|RAMTMP2[3]
--operation mode is normal

G1_RAMTMP2[3]_lut_out = A1L64 & (G1L59 # G1_RAMTMP2[3] & Y1_q_a[6]) # !A1L64 & G1_RAMTMP2[3] & Y1_q_a[6];
G1_RAMTMP2[3] = DFFEA(G1_RAMTMP2[3]_lut_out, !CLK, VCC, , G1L92, , );


--W2_q_b[2] is dram:inst14|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|q_b[2]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 2048, Port A Width: 1, Port B Depth: 2048, Port B Width: 1
--Port A Logical Depth: 2048, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
W2_q_b[2]_PORT_A_data_in = T2_data[2];
W2_q_b[2]_PORT_A_data_in_reg = DFFE(W2_q_b[2]_PORT_A_data_in, W2_q_b[2]_clock_0, , , );
W2_q_b[2]_PORT_A_address = BUS(T2_cnt2[0], T2_cnt2[1], T2_cnt2[2], T2_cnt2[3], T2_cnt2[4], T2_cnt2[5], T2_cnt2[6], T2_cnt2[7], T2_cnt2[8], T2_cnt2[9], T2_cnt2[10]);
W2_q_b[2]_PORT_A_address_reg = DFFE(W2_q_b[2]_PORT_A_address, W2_q_b[2]_clock_0, , , );
W2_q_b[2]_PORT_B_address = BUS(L1_COUNTER[0], L1_COUNTER[1], L1_COUNTER[2], L1_COUNTER[3], L1_COUNTER[4], L1_COUNTER[5], L1_COUNTER[6], L1_COUNTER[7], L1_COUNTER[8], L1_COUNTER[9], L1_COUNTER[10]);
W2_q_b[2]_PORT_B_address_reg = DFFE(W2_q_b[2]_PORT_B_address, W2_q_b[2]_clock_1, , , );
W2_q_b[2]_PORT_A_write_enable = VCC;
W2_q_b[2]_PORT_A_write_enable_reg = DFFE(W2_q_b[2]_PORT_A_write_enable, W2_q_b[2]_clock_0, , , );
W2_q_b[2]_PORT_B_read_enable = VCC;
W2_q_b[2]_PORT_B_read_enable_reg = DFFE(W2_q_b[2]_PORT_B_read_enable, W2_q_b[2]_clock_1, , , );
W2_q_b[2]_clock_0 = CLK;
W2_q_b[2]_clock_1 = CLK;
W2_q_b[2]_PORT_B_data_out = MEMORY(W2_q_b[2]_PORT_A_data_in_reg, , W2_q_b[2]_PORT_A_address_reg, W2_q_b[2]_PORT_B_address_reg, W2_q_b[2]_PORT_A_write_enable_reg, W2_q_b[2]_PORT_B_read_enable_reg, , , W2_q_b[2]_clock_0, W2_q_b[2]_clock_1, , , , );
W2_q_b[2] = W2_q_b[2]_PORT_B_data_out[0];


--G1_RAMTMP5[2] is BUS_1:inst5|RAMTMP5[2]
--operation mode is normal

G1_RAMTMP5[2]_lut_out = A1L74 & (G1L69 # G1_RAMTMP5[2] & Y1_q_a[5]) # !A1L74 & G1_RAMTMP5[2] & Y1_q_a[5];
G1_RAMTMP5[2] = DFFEA(G1_RAMTMP5[2]_lut_out, !CLK, VCC, , G1L92, , );


--W1_q_b[2] is dram:inst|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|q_b[2]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 2048, Port A Width: 1, Port B Depth: 2048, Port B Width: 1
--Port A Logical Depth: 2048, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
W1_q_b[2]_PORT_A_data_in = T1_data[2];
W1_q_b[2]_PORT_A_data_in_reg = DFFE(W1_q_b[2]_PORT_A_data_in, W1_q_b[2]_clock_0, , , );
W1_q_b[2]_PORT_A_address = BUS(T1_cnt2[0], T1_cnt2[1], T1_cnt2[2], T1_cnt2[3], T1_cnt2[4], T1_cnt2[5], T1_cnt2[6], T1_cnt2[7], T1_cnt2[8], T1_cnt2[9], T1_cnt2[10]);
W1_q_b[2]_PORT_A_address_reg = DFFE(W1_q_b[2]_PORT_A_address, W1_q_b[2]_clock_0, , , );
W1_q_b[2]_PORT_B_address = BUS(L1_COUNTER[0], L1_COUNTER[1], L1_COUNTER[2], L1_COUNTER[3], L1_COUNTER[4], L1_COUNTER[5], L1_COUNTER[6], L1_COUNTER[7], L1_COUNTER[8], L1_COUNTER[9], L1_COUNTER[10]);
W1_q_b[2]_PORT_B_address_reg = DFFE(W1_q_b[2]_PORT_B_address, W1_q_b[2]_clock_1, , , );
W1_q_b[2]_PORT_A_write_enable = VCC;
W1_q_b[2]_PORT_A_write_enable_reg = DFFE(W1_q_b[2]_PORT_A_write_enable, W1_q_b[2]_clock_0, , , );
W1_q_b[2]_PORT_B_read_enable = VCC;
W1_q_b[2]_PORT_B_read_enable_reg = DFFE(W1_q_b[2]_PORT_B_read_enable, W1_q_b[2]_clock_1, , , );
W1_q_b[2]_clock_0 = CLK;
W1_q_b[2]_clock_1 = CLK;
W1_q_b[2]_PORT_B_data_out = MEMORY(W1_q_b[2]_PORT_A_data_in_reg, , W1_q_b[2]_PORT_A_address_reg, W1_q_b[2]_PORT_B_address_reg, W1_q_b[2]_PORT_A_write_enable_reg, W1_q_b[2]_PORT_B_read_enable_reg, , , W1_q_b[2]_clock_0, W1_q_b[2]_clock_1, , , , );
W1_q_b[2] = W1_q_b[2]_PORT_B_data_out[0];


--G1_RAMTMP2[2] is BUS_1:inst5|RAMTMP2[2]
--operation mode is normal

G1_RAMTMP2[2]_lut_out = A1L74 & (G1L59 # G1_RAMTMP2[2] & Y1_q_a[6]) # !A1L74 & G1_RAMTMP2[2] & Y1_q_a[6];
G1_RAMTMP2[2] = DFFEA(G1_RAMTMP2[2]_lut_out, !CLK, VCC, , G1L92, , );


--W2_q_b[1] is dram:inst14|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|q_b[1]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 2048, Port A Width: 1, Port B Depth: 2048, Port B Width: 1
--Port A Logical Depth: 2048, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
W2_q_b[1]_PORT_A_data_in = T2_data[1];
W2_q_b[1]_PORT_A_data_in_reg = DFFE(W2_q_b[1]_PORT_A_data_in, W2_q_b[1]_clock_0, , , );
W2_q_b[1]_PORT_A_address = BUS(T2_cnt2[0], T2_cnt2[1], T2_cnt2[2], T2_cnt2[3], T2_cnt2[4], T2_cnt2[5], T2_cnt2[6], T2_cnt2[7], T2_cnt2[8], T2_cnt2[9], T2_cnt2[10]);
W2_q_b[1]_PORT_A_address_reg = DFFE(W2_q_b[1]_PORT_A_address, W2_q_b[1]_clock_0, , , );