wave.map.eqn

数字示波器的FPGA实现 VHDL编写 Quartus7.1测试通过

F1_REG_Q[19] = DFFEA(F1_REG_Q[19]_lut_out, K1_CLK, !G1_TMP, , , , );


--N1L9 is VOLTAGE_CONV:inst12|add~5
--operation mode is arithmetic

N1L9_carry_eqn = N1L8;
N1L9 = W2_q_b[4] $ G1_RAMTMP5[4] $ !N1L9_carry_eqn;

--N1L01 is VOLTAGE_CONV:inst12|add~5COUT
--operation mode is arithmetic

N1L01 = CARRY(W2_q_b[4] & (G1_RAMTMP5[4] # !N1L8) # !W2_q_b[4] & G1_RAMTMP5[4] & !N1L8);


--N2L9 is VOLTAGE_CONV:inst15|add~5
--operation mode is arithmetic

N2L9_carry_eqn = N2L8;
N2L9 = W1_q_b[4] $ G1_RAMTMP2[4] $ !N2L9_carry_eqn;

--N2L01 is VOLTAGE_CONV:inst15|add~5COUT
--operation mode is arithmetic

N2L01 = CARRY(W1_q_b[4] & (G1_RAMTMP2[4] # !N2L8) # !W1_q_b[4] & G1_RAMTMP2[4] & !N2L8);


--F1_REG_Q[18] is generator_accB:inst4|REG_Q[18]
--operation mode is normal

F1_REG_Q[18]_lut_out = F1L73 & (F1L76 # !F1L34 # !F1L14);
F1_REG_Q[18] = DFFEA(F1_REG_Q[18]_lut_out, K1_CLK, !G1_TMP, , , , );


--N1L7 is VOLTAGE_CONV:inst12|add~4
--operation mode is arithmetic

N1L7_carry_eqn = N1L6;
N1L7 = W2_q_b[3] $ G1_RAMTMP5[3] $ N1L7_carry_eqn;

--N1L8 is VOLTAGE_CONV:inst12|add~4COUT
--operation mode is arithmetic

N1L8 = CARRY(W2_q_b[3] & !G1_RAMTMP5[3] & !N1L6 # !W2_q_b[3] & (!N1L6 # !G1_RAMTMP5[3]));


--N2L7 is VOLTAGE_CONV:inst15|add~4
--operation mode is arithmetic

N2L7_carry_eqn = N2L6;
N2L7 = W1_q_b[3] $ G1_RAMTMP2[3] $ N2L7_carry_eqn;

--N2L8 is VOLTAGE_CONV:inst15|add~4COUT
--operation mode is arithmetic

N2L8 = CARRY(W1_q_b[3] & !G1_RAMTMP2[3] & !N2L6 # !W1_q_b[3] & (!N2L6 # !G1_RAMTMP2[3]));


--F1_REG_Q[17] is generator_accB:inst4|REG_Q[17]
--operation mode is normal

F1_REG_Q[17]_lut_out = F1L53 & (F1L76 # !F1L34 # !F1L14);
F1_REG_Q[17] = DFFEA(F1_REG_Q[17]_lut_out, K1_CLK, !G1_TMP, , , , );


--N1L5 is VOLTAGE_CONV:inst12|add~3
--operation mode is arithmetic

N1L5_carry_eqn = N1L4;
N1L5 = W2_q_b[2] $ G1_RAMTMP5[2] $ !N1L5_carry_eqn;

--N1L6 is VOLTAGE_CONV:inst12|add~3COUT
--operation mode is arithmetic

N1L6 = CARRY(W2_q_b[2] & (G1_RAMTMP5[2] # !N1L4) # !W2_q_b[2] & G1_RAMTMP5[2] & !N1L4);


--N2L5 is VOLTAGE_CONV:inst15|add~3
--operation mode is arithmetic

N2L5_carry_eqn = N2L4;
N2L5 = W1_q_b[2] $ G1_RAMTMP2[2] $ !N2L5_carry_eqn;

--N2L6 is VOLTAGE_CONV:inst15|add~3COUT
--operation mode is arithmetic

N2L6 = CARRY(W1_q_b[2] & (G1_RAMTMP2[2] # !N2L4) # !W1_q_b[2] & G1_RAMTMP2[2] & !N2L4);


--F1_REG_Q[16] is generator_accB:inst4|REG_Q[16]
--operation mode is normal

F1_REG_Q[16]_lut_out = F1L33 & (F1L76 # !F1L34 # !F1L14);
F1_REG_Q[16] = DFFEA(F1_REG_Q[16]_lut_out, K1_CLK, !G1_TMP, , , , );


--N1L3 is VOLTAGE_CONV:inst12|add~2
--operation mode is arithmetic

N1L3_carry_eqn = N1L2;
N1L3 = W2_q_b[1] $ G1_RAMTMP5[1] $ N1L3_carry_eqn;

--N1L4 is VOLTAGE_CONV:inst12|add~2COUT
--operation mode is arithmetic

N1L4 = CARRY(W2_q_b[1] & !G1_RAMTMP5[1] & !N1L2 # !W2_q_b[1] & (!N1L2 # !G1_RAMTMP5[1]));


--N2L3 is VOLTAGE_CONV:inst15|add~2
--operation mode is arithmetic

N2L3_carry_eqn = N2L2;
N2L3 = W1_q_b[1] $ G1_RAMTMP2[1] $ N2L3_carry_eqn;

--N2L4 is VOLTAGE_CONV:inst15|add~2COUT
--operation mode is arithmetic

N2L4 = CARRY(W1_q_b[1] & !G1_RAMTMP2[1] & !N2L2 # !W1_q_b[1] & (!N2L2 # !G1_RAMTMP2[1]));


--F1_REG_Q[15] is generator_accB:inst4|REG_Q[15]
--operation mode is normal

F1_REG_Q[15]_lut_out = F1L13 & (F1L76 # !F1L34 # !F1L14);
F1_REG_Q[15] = DFFEA(F1_REG_Q[15]_lut_out, K1_CLK, !G1_TMP, , , , );


--N1L1 is VOLTAGE_CONV:inst12|add~1
--operation mode is arithmetic

N1L1 = W2_q_b[0] $ G1_RAMTMP5[0];

--N1L2 is VOLTAGE_CONV:inst12|add~1COUT
--operation mode is arithmetic

N1L2 = CARRY(W2_q_b[0] & G1_RAMTMP5[0]);


--N2L1 is VOLTAGE_CONV:inst15|add~1
--operation mode is arithmetic

N2L1 = W1_q_b[0] $ G1_RAMTMP2[0];

--N2L2 is VOLTAGE_CONV:inst15|add~1COUT
--operation mode is arithmetic

N2L2 = CARRY(W1_q_b[0] & G1_RAMTMP2[0]);


--F1_REG_Q[14] is generator_accB:inst4|REG_Q[14]
--operation mode is normal

F1_REG_Q[14]_lut_out = F1L92 & (F1L76 # !F1L34 # !F1L14);
F1_REG_Q[14] = DFFEA(F1_REG_Q[14]_lut_out, K1_CLK, !G1_TMP, , , , );


--F1_REG_Q[13] is generator_accB:inst4|REG_Q[13]
--operation mode is normal

F1_REG_Q[13]_lut_out = F1L72 & (F1L76 # !F1L34 # !F1L14);
F1_REG_Q[13] = DFFEA(F1_REG_Q[13]_lut_out, K1_CLK, !G1_TMP, , , , );


--F1_REG_Q[12] is generator_accB:inst4|REG_Q[12]
--operation mode is normal

F1_REG_Q[12]_lut_out = F1L52 & (F1L76 # !F1L34 # !F1L14);
F1_REG_Q[12] = DFFEA(F1_REG_Q[12]_lut_out, K1_CLK, !G1_TMP, , , , );


--G1_P0_OUT[7] is BUS_1:inst5|P0_OUT[7]
--operation mode is normal

G1_P0_OUT[7]_lut_out = H1_TEMP[15] & (G1L02 # !G1L29) # !H1_TEMP[15] & G1L02 & G1L29;
G1_P0_OUT[7]_sload_eqn = (G1L19 & H1_TEMP[7]) # (!G1L19 & G1_P0_OUT[7]_lut_out);
G1_P0_OUT[7] = DFFEA(G1_P0_OUT[7]_sload_eqn, CLK, VCC, , G1L82, , );


--G1_GX is BUS_1:inst5|GX
--operation mode is normal

G1_GX_lut_out = G1L82 & (G1L19 # !G1L29 # !G1L39);
G1_GX = DFFEA(G1_GX_lut_out, CLK, VCC, , , , );


--G1_P0_OUT[6] is BUS_1:inst5|P0_OUT[6]
--operation mode is normal

G1_P0_OUT[6]_lut_out = H1_TEMP[14] & (G1L12 # !G1L29) # !H1_TEMP[14] & G1L12 & G1L29;
G1_P0_OUT[6]_sload_eqn = (G1L19 & H1_TEMP[6]) # (!G1L19 & G1_P0_OUT[6]_lut_out);
G1_P0_OUT[6] = DFFEA(G1_P0_OUT[6]_sload_eqn, CLK, VCC, , G1L82, , );


--G1_P0_OUT[5] is BUS_1:inst5|P0_OUT[5]
--operation mode is normal

G1_P0_OUT[5]_lut_out = H1_TEMP[13] & (G1L22 # !G1L29) # !H1_TEMP[13] & G1L22 & G1L29;
G1_P0_OUT[5]_sload_eqn = (G1L19 & H1_TEMP[5]) # (!G1L19 & G1_P0_OUT[5]_lut_out);
G1_P0_OUT[5] = DFFEA(G1_P0_OUT[5]_sload_eqn, CLK, VCC, , G1L82, , );


--G1_P0_OUT[4] is BUS_1:inst5|P0_OUT[4]
--operation mode is normal

G1_P0_OUT[4]_lut_out = H1_TEMP[12] & (G1L32 # !G1L29) # !H1_TEMP[12] & G1L32 & G1L29;
G1_P0_OUT[4]_sload_eqn = (G1L19 & H1_TEMP[4]) # (!G1L19 & G1_P0_OUT[4]_lut_out);
G1_P0_OUT[4] = DFFEA(G1_P0_OUT[4]_sload_eqn, CLK, VCC, , G1L82, , );


--G1_P0_OUT[3] is BUS_1:inst5|P0_OUT[3]
--operation mode is normal

G1_P0_OUT[3]_lut_out = H1_TEMP[11] & (G1L42 # !G1L29) # !H1_TEMP[11] & G1L42 & G1L29;
G1_P0_OUT[3]_sload_eqn = (G1L19 & H1_TEMP[3]) # (!G1L19 & G1_P0_OUT[3]_lut_out);
G1_P0_OUT[3] = DFFEA(G1_P0_OUT[3]_sload_eqn, CLK, VCC, , G1L82, , );


--G1_P0_OUT[2] is BUS_1:inst5|P0_OUT[2]
--operation mode is normal

G1_P0_OUT[2]_lut_out = H1_TEMP[10] & (G1L52 # !G1L29) # !H1_TEMP[10] & G1L52 & G1L29;
G1_P0_OUT[2]_sload_eqn = (G1L19 & H1_TEMP[2]) # (!G1L19 & G1_P0_OUT[2]_lut_out);
G1_P0_OUT[2] = DFFEA(G1_P0_OUT[2]_sload_eqn, CLK, VCC, , G1L82, , );


--G1_P0_OUT[1] is BUS_1:inst5|P0_OUT[1]
--operation mode is normal

G1_P0_OUT[1]_lut_out = H1_TEMP[9] & (G1L62 # !G1L29) # !H1_TEMP[9] & G1L62 & G1L29;
G1_P0_OUT[1]_sload_eqn = (G1L19 & H1_TEMP[1]) # (!G1L19 & G1_P0_OUT[1]_lut_out);
G1_P0_OUT[1] = DFFEA(G1_P0_OUT[1]_sload_eqn, CLK, VCC, , G1L82, , );


--G1_P0_OUT[0] is BUS_1:inst5|P0_OUT[0]
--operation mode is normal

G1_P0_OUT[0]_lut_out = H1_TEMP[8] & (G1L72 # !G1L29) # !H1_TEMP[8] & G1L72 & G1L29;
G1_P0_OUT[0]_sload_eqn = (G1L19 & H1_TEMP[0]) # (!G1L19 & G1_P0_OUT[0]_lut_out);
G1_P0_OUT[0] = DFFEA(G1_P0_OUT[0]_sload_eqn, CLK, VCC, , G1L82, , );


--W2_q_b[7] is dram:inst14|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|q_b[7]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 2048, Port A Width: 1, Port B Depth: 2048, Port B Width: 1
--Port A Logical Depth: 2048, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
W2_q_b[7]_PORT_A_data_in = T2_data[7];
W2_q_b[7]_PORT_A_data_in_reg = DFFE(W2_q_b[7]_PORT_A_data_in, W2_q_b[7]_clock_0, , , );
W2_q_b[7]_PORT_A_address = BUS(T2_cnt2[0], T2_cnt2[1], T2_cnt2[2], T2_cnt2[3], T2_cnt2[4], T2_cnt2[5], T2_cnt2[6], T2_cnt2[7], T2_cnt2[8], T2_cnt2[9], T2_cnt2[10]);
W2_q_b[7]_PORT_A_address_reg = DFFE(W2_q_b[7]_PORT_A_address, W2_q_b[7]_clock_0, , , );
W2_q_b[7]_PORT_B_address = BUS(L1_COUNTER[0], L1_COUNTER[1], L1_COUNTER[2], L1_COUNTER[3], L1_COUNTER[4], L1_COUNTER[5], L1_COUNTER[6], L1_COUNTER[7], L1_COUNTER[8], L1_COUNTER[9], L1_COUNTER[10]);
W2_q_b[7]_PORT_B_address_reg = DFFE(W2_q_b[7]_PORT_B_address, W2_q_b[7]_clock_1, , , );
W2_q_b[7]_PORT_A_write_enable = VCC;
W2_q_b[7]_PORT_A_write_enable_reg = DFFE(W2_q_b[7]_PORT_A_write_enable, W2_q_b[7]_clock_0, , , );
W2_q_b[7]_PORT_B_read_enable = VCC;
W2_q_b[7]_PORT_B_read_enable_reg = DFFE(W2_q_b[7]_PORT_B_read_enable, W2_q_b[7]_clock_1, , , );
W2_q_b[7]_clock_0 = CLK;
W2_q_b[7]_clock_1 = CLK;
W2_q_b[7]_PORT_B_data_out = MEMORY(W2_q_b[7]_PORT_A_data_in_reg, , W2_q_b[7]_PORT_A_address_reg, W2_q_b[7]_PORT_B_address_reg, W2_q_b[7]_PORT_A_write_enable_reg, W2_q_b[7]_PORT_B_read_enable_reg, , , W2_q_b[7]_clock_0, W2_q_b[7]_clock_1, , , , );
W2_q_b[7] = W2_q_b[7]_PORT_B_data_out[0];


--G1_RAMTMP5[7] is BUS_1:inst5|RAMTMP5[7]
--operation mode is normal

G1_RAMTMP5[7]_lut_out = A1L24 & (G1L69 # G1_RAMTMP5[7] & Y1_q_a[5]) # !A1L24 & G1_RAMTMP5[7] & Y1_q_a[5];
G1_RAMTMP5[7] = DFFEA(G1_RAMTMP5[7]_lut_out, !CLK, VCC, , G1L92, , );


--U1L2Q is CONV_SINGLE:inst22|CURRENT_STATE~11
--operation mode is normal

U1L2Q_lut_out = G1_RAMTMP6[0] & (U1L2Q & U1L44 # !U1L1Q);
U1L2Q = DFFEA(U1L2Q_lut_out, CLK, VCC, , , , );


--U1L4Q is CONV_SINGLE:inst22|CURRENT_STATE~13
--operation mode is normal

U1L4Q_lut_out = U1L83 & (U1L4Q # U1L32 & U1L3Q) # !U1L83 & U1L32 & U1L3Q;
U1L4Q = DFFEA(U1L4Q_lut_out, CLK, VCC, , , , );


--U1L1Q is CONV_SINGLE:inst22|CURRENT_STATE~10
--operation mode is normal

U1L1Q_lut_out = !U1L93 & (G1_RAMTMP6[0] # !U1L44 # !U1L2Q);
U1L1Q = DFFEA(U1L1Q_lut_out, CLK, VCC, , , , );


--U1L5Q is CONV_SINGLE:inst22|CURRENT_STATE~14
--operation mode is normal

U1L5Q_lut_out = U1L5Q & (G1_RAMTMP6[0] # U1L4Q & !U1L83) # !U1L5Q & U1L4Q & !U1L83;
U1L5Q = DFFEA(U1L5Q_lut_out, CLK, VCC, , , , );


--U1L7 is CONV_SINGLE:inst22|EN~78
--operation mode is normal

U1L7 = U1L1Q & !U1L5Q;


--U1L6 is CONV_SINGLE:inst22|EN~77
--operation mode is normal

U1L6 = LCELL(U1L7 & (U1L6 # U1L2Q # U1L4Q));


--N1L82 is VOLTAGE_CONV:inst12|LessThan~7
--operation mode is arithmetic

N1L82 = CARRY(N1L31 & W2_q_b[6] & !N1L62 # !N1L31 & (W2_q_b[6] # !N1L62));


--W1_q_b[7] is dram:inst|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|q_b[7]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 2048, Port A Width: 1, Port B Depth: 2048, Port B Width: 1
--Port A Logical Depth: 2048, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
W1_q_b[7]_PORT_A_data_in = T1_data[7];
W1_q_b[7]_PORT_A_data_in_reg = DFFE(W1_q_b[7]_PORT_A_data_in, W1_q_b[7]_clock_0, , , );
W1_q_b[7]_PORT_A_address = BUS(T1_cnt2[0], T1_cnt2[1], T1_cnt2[2], T1_cnt2[3], T1_cnt2[4], T1_cnt2[5], T1_cnt2[6], T1_cnt2[7], T1_cnt2[8], T1_cnt2[9], T1_cnt2[10]);
W1_q_b[7]_PORT_A_address_reg = DFFE(W1_q_b[7]_PORT_A_address, W1_q_b[7]_clock_0, , , );
W1_q_b[7]_PORT_B_address = BUS(L1_COUNTER[0], L1_COUNTER[1], L1_COUNTER[2], L1_COUNTER[3], L1_COUNTER[4], L1_COUNTER[5], L1_COUNTER[6], L1_COUNTER[7], L1_COUNTER[8], L1_COUNTER[9], L1_COUNTER[10]);
W1_q_b[7]_PORT_B_address_reg = DFFE(W1_q_b[7]_PORT_B_address, W1_q_b[7]_clock_1, , , );
W1_q_b[7]_PORT_A_write_enable = VCC;
W1_q_b[7]_PORT_A_write_enable_reg = DFFE(W1_q_b[7]_PORT_A_write_enable, W1_q_b[7]_clock_0, , , );
W1_q_b[7]_PORT_B_read_enable = VCC;
W1_q_b[7]_PORT_B_read_enable_reg = DFFE(W1_q_b[7]_PORT_B_read_enable, W1_q_b[7]_clock_1, , , );
W1_q_b[7]_clock_0 = CLK;
W1_q_b[7]_clock_1 = CLK;
W1_q_b[7]_PORT_B_data_out = MEMORY(W1_q_b[7]_PORT_A_data_in_reg, , W1_q_b[7]_PORT_A_address_reg, W1_q_b[7]_PORT_B_address_reg, W1_q_b[7]_PORT_A_write_enable_reg, W1_q_b[7]_PORT_B_read_enable_reg, , , W1_q_b[7]_clock_0, W1_q_b[7]_clock_1, , , , );
W1_q_b[7] = W1_q_b[7]_PORT_B_data_out[0];