wave.map.eqn

数字示波器的FPGA实现 VHDL编写 Quartus7.1测试通过

--N2_TEMP[0] is VOLTAGE_CONV:inst15|TEMP[0]
--operation mode is normal

N2_TEMP[0]_lut_out = N2L1;
N2_TEMP[0] = DFFEA(N2_TEMP[0]_lut_out, !P1_CLK, !U1L6, , !N2L03, , );


--J1_TEMP_Q_1[2] is generator_reg81:inst7|TEMP_Q_1[2]
--operation mode is normal

J1_TEMP_Q_1[2]_lut_out = F1_REG_Q[14];
J1_TEMP_Q_1[2] = DFFEA(J1_TEMP_Q_1[2]_lut_out, K1_CLK, !G1_TMP, , , , );


--J1_TEMP_Q_1[1] is generator_reg81:inst7|TEMP_Q_1[1]
--operation mode is normal

J1_TEMP_Q_1[1]_lut_out = F1_REG_Q[13];
J1_TEMP_Q_1[1] = DFFEA(J1_TEMP_Q_1[1]_lut_out, K1_CLK, !G1_TMP, , , , );


--J1_TEMP_Q_1[0] is generator_reg81:inst7|TEMP_Q_1[0]
--operation mode is normal

J1_TEMP_Q_1[0]_lut_out = F1_REG_Q[12];
J1_TEMP_Q_1[0] = DFFEA(J1_TEMP_Q_1[0]_lut_out, K1_CLK, !G1_TMP, , , , );


--M1L1 is MAX114:inst11|add~56
--operation mode is normal

M1L1 = M1_cnt[1] & M1_cnt[0];


--M1L03 is MAX114:inst11|Mux~321
--operation mode is normal

M1L03 = M1_cnt[1] & M1_cnt[2] & M1_cnt[0];


--K1_COUNTER[1] is FREDEVIDER8:inst8|COUNTER[1]
--operation mode is normal

K1_COUNTER[1]_lut_out = K1_COUNTER[1] & !K1_COUNTER[0] # !K1_COUNTER[1] & !K1_COUNTER[2] & K1_COUNTER[0];
K1_COUNTER[1] = DFFEA(K1_COUNTER[1]_lut_out, CLK, VCC, , , , );


--K1_COUNTER[0] is FREDEVIDER8:inst8|COUNTER[0]
--operation mode is normal

K1_COUNTER[0]_lut_out = !K1_COUNTER[0];
K1_COUNTER[0] = DFFEA(K1_COUNTER[0]_lut_out, CLK, VCC, , , , );


--K1_COUNTER[2] is FREDEVIDER8:inst8|COUNTER[2]
--operation mode is normal

K1_COUNTER[2]_lut_out = K1_COUNTER[1] & (K1_COUNTER[2] $ K1_COUNTER[0]) # !K1_COUNTER[1] & K1_COUNTER[2] & !K1_COUNTER[0];
K1_COUNTER[2] = DFFEA(K1_COUNTER[2]_lut_out, CLK, VCC, , , , );


--K1L6 is FREDEVIDER8:inst8|reduce_nor~14
--operation mode is normal

K1L6 = !K1_COUNTER[1] & K1_COUNTER[0] & K1_COUNTER[2];


--N1L51 is VOLTAGE_CONV:inst12|add~8
--operation mode is normal

N1L51_carry_eqn = N1L41;
N1L51 = W2_q_b[7] $ G1_RAMTMP5[7] $ N1L51_carry_eqn;


--P1_CLK is FREDEVIDER2:inst13|CLK
--operation mode is normal

P1_CLK_lut_out = !P1_CLK;
P1_CLK = DFFEA(P1_CLK_lut_out, M1_RD, VCC, , , , );


--N1L03 is VOLTAGE_CONV:inst12|LessThan~8
--operation mode is normal

N1L03_carry_eqn = N1L82;
N1L03 = N1L51 & W2_q_b[7] & N1L03_carry_eqn # !N1L51 & (W2_q_b[7] # N1L03_carry_eqn);


--N2L51 is VOLTAGE_CONV:inst15|add~8
--operation mode is normal

N2L51_carry_eqn = N2L41;
N2L51 = W1_q_b[7] $ G1_RAMTMP2[7] $ N2L51_carry_eqn;


--N2L03 is VOLTAGE_CONV:inst15|LessThan~8
--operation mode is normal

N2L03_carry_eqn = N2L82;
N2L03 = N2L51 & W1_q_b[7] & N2L03_carry_eqn # !N2L51 & (W1_q_b[7] # N2L03_carry_eqn);


--F1_REG_Q[21] is generator_accB:inst4|REG_Q[21]
--operation mode is normal

F1_REG_Q[21]_lut_out = F1L34 & (F1L76 # !F1L14);
F1_REG_Q[21] = DFFEA(F1_REG_Q[21]_lut_out, K1_CLK, !G1_TMP, , , , );


--G1_TMP is BUS_1:inst5|TMP
--operation mode is normal

G1_TMP_lut_out = G1_TMP & (Y1_q_a[3] # G1_LATCH_ADDRES[1] & G1L101) # !G1_TMP & G1_LATCH_ADDRES[1] & G1L101;
G1_TMP = DFFEA(G1_TMP_lut_out, !CLK, VCC, , G1L92, , );


--Y1_q_a[2] is BUS_1:inst5|altsyncram:reduce_or_rtl_1|altsyncram_7vi:auto_generated|q_a[2]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
Y1_q_a[2]_PORT_A_address = BUS(A1L34, A1L44, A1L54, A1L64, A1L74, A1L84, A1L94, A1L24);
Y1_q_a[2]_PORT_A_address_reg = DFFE(Y1_q_a[2]_PORT_A_address, Y1_q_a[2]_clock_0, , , );
Y1_q_a[2]_clock_0 = !ALE;
Y1_q_a[2]_PORT_A_data_out = MEMORY(, , Y1_q_a[2]_PORT_A_address_reg, , , , , , Y1_q_a[2]_clock_0, , , , , );
Y1_q_a[2] = Y1_q_a[2]_PORT_A_data_out[0];


--G1_LATCH_ADDRES[0] is BUS_1:inst5|LATCH_ADDRES[0]
--operation mode is normal

G1_LATCH_ADDRES[0]_lut_out = A1L94;
G1_LATCH_ADDRES[0] = DFFEA(G1_LATCH_ADDRES[0]_lut_out, !ALE, VCC, , , , );


--G1_LATCH_ADDRES[6] is BUS_1:inst5|LATCH_ADDRES[6]
--operation mode is normal

G1_LATCH_ADDRES[6]_lut_out = A1L34;
G1_LATCH_ADDRES[6] = DFFEA(G1_LATCH_ADDRES[6]_lut_out, !ALE, VCC, , , , );


--G1_LATCH_ADDRES[5] is BUS_1:inst5|LATCH_ADDRES[5]
--operation mode is normal

G1_LATCH_ADDRES[5]_lut_out = A1L44;
G1_LATCH_ADDRES[5] = DFFEA(G1_LATCH_ADDRES[5]_lut_out, !ALE, VCC, , , , );


--G1_LATCH_ADDRES[4] is BUS_1:inst5|LATCH_ADDRES[4]
--operation mode is normal

G1_LATCH_ADDRES[4]_lut_out = A1L54;
G1_LATCH_ADDRES[4] = DFFEA(G1_LATCH_ADDRES[4]_lut_out, !ALE, VCC, , , , );


--G1_LATCH_ADDRES[7] is BUS_1:inst5|LATCH_ADDRES[7]
--operation mode is normal

G1_LATCH_ADDRES[7]_lut_out = A1L24;
G1_LATCH_ADDRES[7] = DFFEA(G1_LATCH_ADDRES[7]_lut_out, !ALE, VCC, , , , );


--G1L99 is BUS_1:inst5|reduce_nor~170
--operation mode is normal

G1L99 = G1_LATCH_ADDRES[6] & G1_LATCH_ADDRES[5] & G1_LATCH_ADDRES[4] & G1_LATCH_ADDRES[7];


--G1_LATCH_ADDRES[1] is BUS_1:inst5|LATCH_ADDRES[1]
--operation mode is normal

G1_LATCH_ADDRES[1]_lut_out = A1L84;
G1_LATCH_ADDRES[1] = DFFEA(G1_LATCH_ADDRES[1]_lut_out, !ALE, VCC, , , , );


--G1_LATCH_ADDRES[2] is BUS_1:inst5|LATCH_ADDRES[2]
--operation mode is normal

G1_LATCH_ADDRES[2]_lut_out = A1L74;
G1_LATCH_ADDRES[2] = DFFEA(G1_LATCH_ADDRES[2]_lut_out, !ALE, VCC, , , , );


--G1L001 is BUS_1:inst5|reduce_nor~171
--operation mode is normal

G1L001 = G1L99 & G1_LATCH_ADDRES[1] & !G1_LATCH_ADDRES[2];


--G1_LATCH_ADDRES[3] is BUS_1:inst5|LATCH_ADDRES[3]
--operation mode is normal

G1_LATCH_ADDRES[3]_lut_out = A1L64;
G1_LATCH_ADDRES[3] = DFFEA(G1_LATCH_ADDRES[3]_lut_out, !ALE, VCC, , , , );


--G1L49 is BUS_1:inst5|reduce_nor~3
--operation mode is normal

G1L49 = G1_LATCH_ADDRES[0] & G1L001 & !G1_LATCH_ADDRES[3];


--G1L92 is BUS_1:inst5|process2~0
--operation mode is normal

G1L92 = !CS & !WR;


--F1L53 is generator_accB:inst4|add~18
--operation mode is arithmetic

F1L53_carry_eqn = F1L43;
F1L53 = F1_REG_Q[17] $ F1L53_carry_eqn;

--F1L63 is generator_accB:inst4|add~18COUT
--operation mode is arithmetic

F1L63 = CARRY(!F1L43 # !F1_REG_Q[17]);


--F1L73 is generator_accB:inst4|add~19
--operation mode is arithmetic

F1L73_carry_eqn = F1L63;
F1L73 = F1_REG_Q[18] $ !F1L73_carry_eqn;

--F1L83 is generator_accB:inst4|add~19COUT
--operation mode is arithmetic

F1L83 = CARRY(F1_REG_Q[18] & !F1L63);


--F1L93 is generator_accB:inst4|add~20
--operation mode is arithmetic

F1L93_carry_eqn = F1L83;
F1L93 = F1_REG_Q[19] $ F1L93_carry_eqn;

--F1L04 is generator_accB:inst4|add~20COUT
--operation mode is arithmetic

F1L04 = CARRY(!F1L83 # !F1_REG_Q[19]);


--F1L76 is generator_accB:inst4|REG_Q~538
--operation mode is normal

F1L76 = !F1L53 & !F1L73 & !F1L93;


--F1L14 is generator_accB:inst4|add~21
--operation mode is arithmetic

F1L14_carry_eqn = F1L04;
F1L14 = F1_REG_Q[20] $ !F1L14_carry_eqn;

--F1L24 is generator_accB:inst4|add~21COUT
--operation mode is arithmetic

F1L24 = CARRY(F1_REG_Q[20] & !F1L04);


--F1L34 is generator_accB:inst4|add~22
--operation mode is normal

F1L34_carry_eqn = F1L24;
F1L34 = F1_REG_Q[21] $ F1L34_carry_eqn;


--F1L07 is generator_accB:inst4|TEMP~0
--operation mode is normal

F1L07 = !G1_TMP & !F1L76 & F1L14 & F1L34;


--N1L31 is VOLTAGE_CONV:inst12|add~7
--operation mode is arithmetic

N1L31_carry_eqn = N1L21;
N1L31 = W2_q_b[6] $ G1_RAMTMP5[6] $ !N1L31_carry_eqn;

--N1L41 is VOLTAGE_CONV:inst12|add~7COUT
--operation mode is arithmetic

N1L41 = CARRY(W2_q_b[6] & (G1_RAMTMP5[6] # !N1L21) # !W2_q_b[6] & G1_RAMTMP5[6] & !N1L21);


--N2L31 is VOLTAGE_CONV:inst15|add~7
--operation mode is arithmetic

N2L31_carry_eqn = N2L21;
N2L31 = W1_q_b[6] $ G1_RAMTMP2[6] $ !N2L31_carry_eqn;

--N2L41 is VOLTAGE_CONV:inst15|add~7COUT
--operation mode is arithmetic

N2L41 = CARRY(W1_q_b[6] & (G1_RAMTMP2[6] # !N2L21) # !W1_q_b[6] & G1_RAMTMP2[6] & !N2L21);


--F1_REG_Q[20] is generator_accB:inst4|REG_Q[20]
--operation mode is normal

F1_REG_Q[20]_lut_out = F1L14 & (F1L76 # !F1L34);
F1_REG_Q[20] = DFFEA(F1_REG_Q[20]_lut_out, K1_CLK, !G1_TMP, , , , );


--N1L11 is VOLTAGE_CONV:inst12|add~6
--operation mode is arithmetic

N1L11_carry_eqn = N1L01;
N1L11 = W2_q_b[5] $ G1_RAMTMP5[5] $ N1L11_carry_eqn;

--N1L21 is VOLTAGE_CONV:inst12|add~6COUT
--operation mode is arithmetic

N1L21 = CARRY(W2_q_b[5] & !G1_RAMTMP5[5] & !N1L01 # !W2_q_b[5] & (!N1L01 # !G1_RAMTMP5[5]));


--N2L11 is VOLTAGE_CONV:inst15|add~6
--operation mode is arithmetic

N2L11_carry_eqn = N2L01;
N2L11 = W1_q_b[5] $ G1_RAMTMP2[5] $ N2L11_carry_eqn;

--N2L21 is VOLTAGE_CONV:inst15|add~6COUT
--operation mode is arithmetic

N2L21 = CARRY(W1_q_b[5] & !G1_RAMTMP2[5] & !N2L01 # !W1_q_b[5] & (!N2L01 # !G1_RAMTMP2[5]));


--F1_REG_Q[19] is generator_accB:inst4|REG_Q[19]
--operation mode is normal

F1_REG_Q[19]_lut_out = F1L93 & (F1L76 # !F1L34 # !F1L14);