scanwave.map.rpt

数字示波器的FPGA实现 VHDL编写 Quartus7.1测试通过

+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary                                                                                                                                                                        ;
+---------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+-------------------+
; Name                                                                                  ; Type ; Mode             ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size  ; MIF               ;
+---------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+-------------------+
; BUS_1:inst5|altsyncram:reduce_or_rtl_2|altsyncram_ccj:auto_generated|ALTSYNCRAM       ; AUTO ; ROM              ; 256          ; 8            ; --           ; --           ; 2048  ; SCANWAVE0.rtl.mif ;
; dram:inst14|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|ALTSYNCRAM ; M4K  ; Simple Dual Port ; 2048         ; 8            ; 2048         ; 8            ; 16384 ; None              ;
; dram:inst|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|ALTSYNCRAM   ; M4K  ; Simple Dual Port ; 2048         ; 8            ; 2048         ; 8            ; 16384 ; None              ;
+---------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+-------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 4.1 Build 181 06/29/2004 SJ Full Version
    Info: Processing started: Fri Sep 02 10:13:47 2005
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off scanwave -c scanwave
Info: Found 2 design units, including 1 entities, in source file MUX2_1.vhd
    Info: Found design unit 1: MUX2_1-ART
    Info: Found entity 1: MUX2_1
Info: Found 2 design units, including 1 entities, in source file AD_SRAM.vhd
    Info: Found design unit 1: AD_SRAM-ART
    Info: Found entity 1: AD_SRAM
Info: Found 2 design units, including 1 entities, in source file BUS_1.vhd
    Info: Found design unit 1: BUS_1-ART
    Info: Found entity 1: BUS_1
Info: Found 2 design units, including 1 entities, in source file BUSTRI.vhd
    Info: Found design unit 1: bustri-SYN
    Info: Found entity 1: bustri
Info: Found 2 design units, including 1 entities, in source file CONV_SINGLE.vhd
    Info: Found design unit 1: CONV_SINGLE-ART
    Info: Found entity 1: CONV_SINGLE
Info: Found 2 design units, including 1 entities, in source file fredevider8.vhd
    Info: Found design unit 1: FREDEVIDER8-ART
    Info: Found entity 1: FREDEVIDER8
Info: Found 2 design units, including 1 entities, in source file generator_accb.vhd
    Info: Found design unit 1: generator_accB-acc_arch
    Info: Found entity 1: generator_accB
Info: Found 2 design units, including 1 entities, in source file GENERATOR_ADD.vhd
    Info: Found design unit 1: generator_add-add_anGen_arch
    Info: Found entity 1: generator_add
Info: Found 2 design units, including 1 entities, in source file generator_reg8.vhd
    Info: Found design unit 1: generator_reg8-reg_arch8
    Info: Found entity 1: generator_reg8
Info: Found 2 design units, including 1 entities, in source file generator_reg81.vhd
    Info: Found design unit 1: generator_reg81-reg_arch8
    Info: Found entity 1: generator_reg81
Info: Found 2 design units, including 1 entities, in source file GET_RDADDR.VHD
    Info: Found design unit 1: GET_RDADDR-ART
    Info: Found entity 1: GET_RDADDR
Info: Found 2 design units, including 1 entities, in source file max114.vhd
    Info: Found design unit 1: MAX114-BEHAV
    Info: Found entity 1: MAX114
Info: Found 2 design units, including 1 entities, in source file VOLTAGE_CONV.vhd
    Info: Found design unit 1: VOLTAGE_CONV-ART
    Info: Found entity 1: VOLTAGE_CONV
Info: Found 1 design units, including 1 entities, in source file SCANWAVE.bdf
    Info: Found entity 1: SCANWAVE
Info: Found 2 design units, including 1 entities, in source file fredevider2.vhd
    Info: Found design unit 1: FREDEVIDER2-ART
    Info: Found entity 1: FREDEVIDER2
Info: Found 2 design units, including 1 entities, in source file MUX2_3.vhd
    Info: Found design unit 1: MUX2_3-ART
    Info: Found entity 1: MUX2_3
Info: Found 2 design units, including 1 entities, in source file freq_count.vhd
    Info: Found design unit 1: FREQ_COUNT-ART
    Info: Found entity 1: FREQ_COUNT
Info: Found 2 design units, including 1 entities, in source file fredevider10.vhd
    Info: Found design unit 1: FREDEVIDER10-ART
    Info: Found entity 1: FREDEVIDER10
Info: Found 2 design units, including 1 entities, in source file AMPL_COUNT.vhd
    Info: Found design unit 1: AMPL_COUNT-ART
    Info: Found entity 1: AMPL_COUNT
Info: Found 2 design units, including 1 entities, in source file DA5180.vhd
    Info: Found design unit 1: DA5180-ART
    Info: Found entity 1: DA5180
Warning: VHDL Variable Declaration warning at max114.vhd(20): ignored initial value expression for variable cnt
Warning: VHDL Variable Declaration warning at DA5180.vhd(19): ignored initial value expression for variable cnt
Info: VHDL Case Statement information at DA5180.vhd(33): OTHERS choice is never selected
Warning: VHDL Selected Signal Assignment warning at MUX2_3.vhd(11): Selected Signal Assignment choices do not cover all possible values of expression
Info: Using design file dram.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: dram-SYN
    Info: Found entity 1: dram
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus41/libraries/megafunctions/altsyncram.tdf
    Info: Found entity 1: altsyncram
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_3771.tdf
    Info: Found entity 1: altsyncram_3771
Warning: VHDL Signal Declaration warning at CONV_SINGLE.vhd(18): ignored default value for signal current_state
Warning: VHDL Signal Declaration warning at CONV_SINGLE.vhd(18): ignored default value for signal next_state
Warning: VHDL Process Statement warning at CONV_SINGLE.vhd(24): signal current_state is in statement, but is not in sensitivity list
Info: VHDL Case Statement information at CONV_SINGLE.vhd(46): OTHERS choice is never selected
Warning: VHDL Process Statement warning at CONV_SINGLE.vhd(22): signal or variable en may not be assigned a new value in every possible path through the Process Statement. Signal or variable en holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: VHDL Process Statement warning at CONV_SINGLE.vhd(22): signal or variable trigger may not be assigned a new value in every possible path through the Process Statement. Signal or variable trigger holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: VHDL Process Statement warning at CONV_SINGLE.vhd(22): signal or variable temp may not be assigned a new value in every possible path through the Process Statement. Signal or variable temp holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus41/libraries/megafunctions/lpm_bustri.tdf
    Info: Found entity 1: lpm_bustri
Info: Ignored 9 buffer(s)
    Info: Ignored 9 SOFT buffer(s)
Warning: Created node BUS_1:inst5|reduce_or~32 as a ROM by generating altsyncram megafunction to implement register logic with M512 or M4K memory block. Power-up state differs from the original design.
Info: Inferred 3 megafunctions from design logic
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=10) from the following logic: DA5180:inst3|COUNT[0]~0
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=17) from the following logic: FREQ_COUNT:inst6|COUNT2[0]~0
    Info: Inferred altsyncram megafunction (OPERATION_MODE=ROM, NUMWORDS_A=256, WIDTH_A=8) from the following design logic: BUS_1:inst5|reduce_or~32
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus41/libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Info: Found 1 design units, including 1 entities, in source file db/cntr_pt6.tdf
    Info: Found entity 1: cntr_pt6
Info: Found 1 design units, including 1 entities, in source file db/cntr_e08.tdf
    Info: Found entity 1: cntr_e08
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_ccj.tdf
    Info: Found entity 1: altsyncram_ccj
Info: State machine |SCANWAVE|CONV_SINGLE:inst22|CURRENT_STATE contains 5 states and 0 state bits
Info: Selected Auto state machine encoding method for state machine |SCANWAVE|CONV_SINGLE:inst22|CURRENT_STATE
Info: Encoding result for state machine |SCANWAVE|CONV_SINGLE:inst22|CURRENT_STATE
    Info: Completed encoding using 5 state bits
        Info: Encoded state bit CONV_SINGLE:inst22|CURRENT_STATE~14
        Info: Encoded state bit CONV_SINGLE:inst22|CURRENT_STATE~13
        Info: Encoded state bit CONV_SINGLE:inst22|CURRENT_STATE~12
        Info: Encoded state bit CONV_SINGLE:inst22|CURRENT_STATE~11
        Info: Encoded state bit CONV_SINGLE:inst22|CURRENT_STATE~10
    Info: State |SCANWAVE|CONV_SINGLE:inst22|CURRENT_STATE.st0 uses code string 00000
    Info: State |SCANWAVE|CONV_SINGLE:inst22|CURRENT_STATE.st1 uses code string 00011
    Info: State |SCANWAVE|CONV_SINGLE:inst22|CURRENT_STATE.st2 uses code string 00101
    Info: State |SCANWAVE|CONV_SINGLE:inst22|CURRENT_STATE.st3 uses code string 01001
    Info: State |SCANWAVE|CONV_SINGLE:inst22|CURRENT_STATE.st4 uses code string 10001
Warning: Converted TRI buffer to OR gate or removed OPNDRN
    Warning: Converting TRI node bustri:inst1|lpm_bustri:lpm_bustri_component|din[0] that feeds logic to an OR gate
    Warning: Converting TRI node bustri:inst1|lpm_bustri:lpm_bustri_component|din[1] that feeds logic to an OR gate
    Warning: Converting TRI node bustri:inst1|lpm_bustri:lpm_bustri_component|din[6] that feeds logic to an OR gate
    Warning: Converting TRI node bustri:inst1|lpm_bustri:lpm_bustri_component|din[5] that feeds logic to an OR gate
    Warning: Converting TRI node bustri:inst1|lpm_bustri:lpm_bustri_component|din[4] that feeds logic to an OR gate
    Warning: Converting TRI node bustri:inst1|lpm_bustri:lpm_bustri_component|din[3] that feeds logic to an OR gate
    Warning: Converting TRI node bustri:inst1|lpm_bustri:lpm_bustri_component|din[2] that feeds logic to an OR gate
    Warning: Converting TRI node bustri:inst1|lpm_bustri:lpm_bustri_component|din[7] that feeds logic to an OR gate
Info: Duplicate registers merged to single register
    Info: Duplicate register DA5180:inst3|cnt[1] merged to single register DA5180:inst3|TEMP, power-up level changed
Warning: Output pins are stuck at VCC or GND
    Warning: Pin A1 stuck at GND
    Warning: Pin A0 stuck at GND
    Warning: Pin DACS stuck at GND
    Warning: Pin DAEN stuck at VCC
Info: Registers with preset signals will power-up high
Warning: Design contains 5 input pin(s) that do not drive logic
    Warning: No output dependent on input pin P2[4]
    Warning: No output dependent on input pin P2[3]
    Warning: No output dependent on input pin P2[2]
    Warning: No output dependent on input pin P2[1]
    Warning: No output dependent on input pin P2[0]
Info: Implemented 610 device resources after synthesis - the final resource count might be different
    Info: Implemented 20 input pins
    Info: Implemented 18 output pins
    Info: Implemented 8 bidirectional pins
    Info: Implemented 540 logic cells
    Info: Implemented 24 RAM segments
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 30 warnings
    Info: Processing ended: Fri Sep 02 10:14:01 2005
    Info: Elapsed time: 00:00:14