wave.fit.eqn

数字示波器的FPGA实现 VHDL编写 Quartus7.1测试通过

--F1L06 is generator_accB:inst4|add~17COUT1 at LC_X16_Y5_N0
--operation mode is arithmetic

F1L06_cout_1 = F1_REG_Q[16] & !F1L65;
F1L06 = CARRY(F1L06_cout_1);


--W2_q_b[6] is dram:inst14|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|q_b[6] at M4K_X13_Y9
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 2048, Port A Width: 2, Port B Depth: 2048, Port B Width: 2
--Port A Logical Depth: 2048, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
W2_q_b[6]_PORT_A_data_in = BUS(T2_data[6], T2_data[5]);
W2_q_b[6]_PORT_A_data_in_reg = DFFE(W2_q_b[6]_PORT_A_data_in, W2_q_b[6]_clock_0, , , );
W2_q_b[6]_PORT_A_address = BUS(T2_cnt2[0], T2_cnt2[1], T2_cnt2[2], T2_cnt2[3], T2_cnt2[4], T2_cnt2[5], T2_cnt2[6], T2_cnt2[7], T2_cnt2[8], T2_cnt2[9], T2_cnt2[10]);
W2_q_b[6]_PORT_A_address_reg = DFFE(W2_q_b[6]_PORT_A_address, W2_q_b[6]_clock_0, , , );
W2_q_b[6]_PORT_B_address = BUS(L1_COUNTER[0], L1_COUNTER[1], L1_COUNTER[2], L1_COUNTER[3], L1_COUNTER[4], L1_COUNTER[5], L1_COUNTER[6], L1_COUNTER[7], L1_COUNTER[8], L1_COUNTER[9], L1_COUNTER[10]);
W2_q_b[6]_PORT_B_address_reg = DFFE(W2_q_b[6]_PORT_B_address, W2_q_b[6]_clock_1, , , );
W2_q_b[6]_PORT_A_write_enable = VCC;
W2_q_b[6]_PORT_A_write_enable_reg = DFFE(W2_q_b[6]_PORT_A_write_enable, W2_q_b[6]_clock_0, , , );
W2_q_b[6]_PORT_B_read_enable = VCC;
W2_q_b[6]_PORT_B_read_enable_reg = DFFE(W2_q_b[6]_PORT_B_read_enable, W2_q_b[6]_clock_1, , , );
W2_q_b[6]_clock_0 = GLOBAL(CLK);
W2_q_b[6]_clock_1 = GLOBAL(CLK);
W2_q_b[6]_PORT_B_data_out = MEMORY(W2_q_b[6]_PORT_A_data_in_reg, , W2_q_b[6]_PORT_A_address_reg, W2_q_b[6]_PORT_B_address_reg, W2_q_b[6]_PORT_A_write_enable_reg, W2_q_b[6]_PORT_B_read_enable_reg, , , W2_q_b[6]_clock_0, W2_q_b[6]_clock_1, , , , );
W2_q_b[6] = W2_q_b[6]_PORT_B_data_out[0];

--W2_q_b[5] is dram:inst14|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|q_b[5] at M4K_X13_Y9
W2_q_b[6]_PORT_A_data_in = BUS(T2_data[6], T2_data[5]);
W2_q_b[6]_PORT_A_data_in_reg = DFFE(W2_q_b[6]_PORT_A_data_in, W2_q_b[6]_clock_0, , , );
W2_q_b[6]_PORT_A_address = BUS(T2_cnt2[0], T2_cnt2[1], T2_cnt2[2], T2_cnt2[3], T2_cnt2[4], T2_cnt2[5], T2_cnt2[6], T2_cnt2[7], T2_cnt2[8], T2_cnt2[9], T2_cnt2[10]);
W2_q_b[6]_PORT_A_address_reg = DFFE(W2_q_b[6]_PORT_A_address, W2_q_b[6]_clock_0, , , );
W2_q_b[6]_PORT_B_address = BUS(L1_COUNTER[0], L1_COUNTER[1], L1_COUNTER[2], L1_COUNTER[3], L1_COUNTER[4], L1_COUNTER[5], L1_COUNTER[6], L1_COUNTER[7], L1_COUNTER[8], L1_COUNTER[9], L1_COUNTER[10]);
W2_q_b[6]_PORT_B_address_reg = DFFE(W2_q_b[6]_PORT_B_address, W2_q_b[6]_clock_1, , , );
W2_q_b[6]_PORT_A_write_enable = VCC;
W2_q_b[6]_PORT_A_write_enable_reg = DFFE(W2_q_b[6]_PORT_A_write_enable, W2_q_b[6]_clock_0, , , );
W2_q_b[6]_PORT_B_read_enable = VCC;
W2_q_b[6]_PORT_B_read_enable_reg = DFFE(W2_q_b[6]_PORT_B_read_enable, W2_q_b[6]_clock_1, , , );
W2_q_b[6]_clock_0 = GLOBAL(CLK);
W2_q_b[6]_clock_1 = GLOBAL(CLK);
W2_q_b[6]_PORT_B_data_out = MEMORY(W2_q_b[6]_PORT_A_data_in_reg, , W2_q_b[6]_PORT_A_address_reg, W2_q_b[6]_PORT_B_address_reg, W2_q_b[6]_PORT_A_write_enable_reg, W2_q_b[6]_PORT_B_read_enable_reg, , , W2_q_b[6]_clock_0, W2_q_b[6]_clock_1, , , , );
W2_q_b[5] = W2_q_b[6]_PORT_B_data_out[1];


--G1_RAMTMP5[6] is BUS_1:inst5|RAMTMP5[6] at LC_X10_Y4_N3
--operation mode is normal

G1_RAMTMP5[6]_lut_out = G1L69 & (A1L34 # Y1_q_a[5] & G1_RAMTMP5[6]) # !G1L69 & Y1_q_a[5] & G1_RAMTMP5[6];
G1_RAMTMP5[6] = DFFEA(G1_RAMTMP5[6]_lut_out, !GLOBAL(CLK), VCC, , G1L92, , );


--W1_q_b[6] is dram:inst|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|q_b[6] at M4K_X13_Y6
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 2048, Port A Width: 2, Port B Depth: 2048, Port B Width: 2
--Port A Logical Depth: 2048, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
W1_q_b[6]_PORT_A_data_in = BUS(T1_data[6], T1_data[4]);
W1_q_b[6]_PORT_A_data_in_reg = DFFE(W1_q_b[6]_PORT_A_data_in, W1_q_b[6]_clock_0, , , );
W1_q_b[6]_PORT_A_address = BUS(T1_cnt2[0], T1_cnt2[1], T1_cnt2[2], T1_cnt2[3], T1_cnt2[4], T1_cnt2[5], T1_cnt2[6], T1_cnt2[7], T1_cnt2[8], T1_cnt2[9], T1_cnt2[10]);
W1_q_b[6]_PORT_A_address_reg = DFFE(W1_q_b[6]_PORT_A_address, W1_q_b[6]_clock_0, , , );
W1_q_b[6]_PORT_B_address = BUS(L1_COUNTER[0], L1_COUNTER[1], L1_COUNTER[2], L1_COUNTER[3], L1_COUNTER[4], L1_COUNTER[5], L1_COUNTER[6], L1_COUNTER[7], L1_COUNTER[8], L1_COUNTER[9], L1_COUNTER[10]);
W1_q_b[6]_PORT_B_address_reg = DFFE(W1_q_b[6]_PORT_B_address, W1_q_b[6]_clock_1, , , );
W1_q_b[6]_PORT_A_write_enable = VCC;
W1_q_b[6]_PORT_A_write_enable_reg = DFFE(W1_q_b[6]_PORT_A_write_enable, W1_q_b[6]_clock_0, , , );
W1_q_b[6]_PORT_B_read_enable = VCC;
W1_q_b[6]_PORT_B_read_enable_reg = DFFE(W1_q_b[6]_PORT_B_read_enable, W1_q_b[6]_clock_1, , , );
W1_q_b[6]_clock_0 = GLOBAL(CLK);
W1_q_b[6]_clock_1 = GLOBAL(CLK);
W1_q_b[6]_PORT_B_data_out = MEMORY(W1_q_b[6]_PORT_A_data_in_reg, , W1_q_b[6]_PORT_A_address_reg, W1_q_b[6]_PORT_B_address_reg, W1_q_b[6]_PORT_A_write_enable_reg, W1_q_b[6]_PORT_B_read_enable_reg, , , W1_q_b[6]_clock_0, W1_q_b[6]_clock_1, , , , );
W1_q_b[6] = W1_q_b[6]_PORT_B_data_out[0];

--W1_q_b[4] is dram:inst|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|q_b[4] at M4K_X13_Y6
W1_q_b[6]_PORT_A_data_in = BUS(T1_data[6], T1_data[4]);
W1_q_b[6]_PORT_A_data_in_reg = DFFE(W1_q_b[6]_PORT_A_data_in, W1_q_b[6]_clock_0, , , );
W1_q_b[6]_PORT_A_address = BUS(T1_cnt2[0], T1_cnt2[1], T1_cnt2[2], T1_cnt2[3], T1_cnt2[4], T1_cnt2[5], T1_cnt2[6], T1_cnt2[7], T1_cnt2[8], T1_cnt2[9], T1_cnt2[10]);
W1_q_b[6]_PORT_A_address_reg = DFFE(W1_q_b[6]_PORT_A_address, W1_q_b[6]_clock_0, , , );
W1_q_b[6]_PORT_B_address = BUS(L1_COUNTER[0], L1_COUNTER[1], L1_COUNTER[2], L1_COUNTER[3], L1_COUNTER[4], L1_COUNTER[5], L1_COUNTER[6], L1_COUNTER[7], L1_COUNTER[8], L1_COUNTER[9], L1_COUNTER[10]);
W1_q_b[6]_PORT_B_address_reg = DFFE(W1_q_b[6]_PORT_B_address, W1_q_b[6]_clock_1, , , );
W1_q_b[6]_PORT_A_write_enable = VCC;
W1_q_b[6]_PORT_A_write_enable_reg = DFFE(W1_q_b[6]_PORT_A_write_enable, W1_q_b[6]_clock_0, , , );
W1_q_b[6]_PORT_B_read_enable = VCC;
W1_q_b[6]_PORT_B_read_enable_reg = DFFE(W1_q_b[6]_PORT_B_read_enable, W1_q_b[6]_clock_1, , , );
W1_q_b[6]_clock_0 = GLOBAL(CLK);
W1_q_b[6]_clock_1 = GLOBAL(CLK);
W1_q_b[6]_PORT_B_data_out = MEMORY(W1_q_b[6]_PORT_A_data_in_reg, , W1_q_b[6]_PORT_A_address_reg, W1_q_b[6]_PORT_B_address_reg, W1_q_b[6]_PORT_A_write_enable_reg, W1_q_b[6]_PORT_B_read_enable_reg, , , W1_q_b[6]_clock_0, W1_q_b[6]_clock_1, , , , );
W1_q_b[4] = W1_q_b[6]_PORT_B_data_out[1];


--G1_RAMTMP2[6] is BUS_1:inst5|RAMTMP2[6] at LC_X17_Y5_N0
--operation mode is normal

G1_RAMTMP2[6]_lut_out = Y1_q_a[6] & (G1_RAMTMP2[6] # G1L59 & A1L34) # !Y1_q_a[6] & G1L59 & A1L34;
G1_RAMTMP2[6] = DFFEA(G1_RAMTMP2[6]_lut_out, !GLOBAL(CLK), VCC, , G1L92, , );


--G1_RAMTMP5[5] is BUS_1:inst5|RAMTMP5[5] at LC_X17_Y5_N6
--operation mode is normal

G1_RAMTMP5[5]_lut_out = G1_RAMTMP5[5] & (Y1_q_a[5] # G1L69 & A1L44) # !G1_RAMTMP5[5] & G1L69 & A1L44;
G1_RAMTMP5[5] = DFFEA(G1_RAMTMP5[5]_lut_out, !GLOBAL(CLK), VCC, , G1L92, , );


--G1_RAMTMP2[5] is BUS_1:inst5|RAMTMP2[5] at LC_X17_Y5_N8
--operation mode is normal

G1_RAMTMP2[5]_lut_out = Y1_q_a[6] & (G1_RAMTMP2[5] # G1L59 & A1L44) # !Y1_q_a[6] & G1L59 & A1L44;
G1_RAMTMP2[5] = DFFEA(G1_RAMTMP2[5]_lut_out, !GLOBAL(CLK), VCC, , G1L92, , );


--W2_q_b[4] is dram:inst14|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|q_b[4] at M4K_X13_Y7
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 2048, Port A Width: 2, Port B Depth: 2048, Port B Width: 2
--Port A Logical Depth: 2048, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
W2_q_b[4]_PORT_A_data_in = BUS(T2_data[4], T2_data[1]);
W2_q_b[4]_PORT_A_data_in_reg = DFFE(W2_q_b[4]_PORT_A_data_in, W2_q_b[4]_clock_0, , , );
W2_q_b[4]_PORT_A_address = BUS(T2_cnt2[0], T2_cnt2[1], T2_cnt2[2], T2_cnt2[3], T2_cnt2[4], T2_cnt2[5], T2_cnt2[6], T2_cnt2[7], T2_cnt2[8], T2_cnt2[9], T2_cnt2[10]);
W2_q_b[4]_PORT_A_address_reg = DFFE(W2_q_b[4]_PORT_A_address, W2_q_b[4]_clock_0, , , );
W2_q_b[4]_PORT_B_address = BUS(L1_COUNTER[0], L1_COUNTER[1], L1_COUNTER[2], L1_COUNTER[3], L1_COUNTER[4], L1_COUNTER[5], L1_COUNTER[6], L1_COUNTER[7], L1_COUNTER[8], L1_COUNTER[9], L1_COUNTER[10]);
W2_q_b[4]_PORT_B_address_reg = DFFE(W2_q_b[4]_PORT_B_address, W2_q_b[4]_clock_1, , , );
W2_q_b[4]_PORT_A_write_enable = VCC;
W2_q_b[4]_PORT_A_write_enable_reg = DFFE(W2_q_b[4]_PORT_A_write_enable, W2_q_b[4]_clock_0, , , );
W2_q_b[4]_PORT_B_read_enable = VCC;
W2_q_b[4]_PORT_B_read_enable_reg = DFFE(W2_q_b[4]_PORT_B_read_enable, W2_q_b[4]_clock_1, , , );
W2_q_b[4]_clock_0 = GLOBAL(CLK);
W2_q_b[4]_clock_1 = GLOBAL(CLK);
W2_q_b[4]_PORT_B_data_out = MEMORY(W2_q_b[4]_PORT_A_data_in_reg, , W2_q_b[4]_PORT_A_address_reg, W2_q_b[4]_PORT_B_address_reg, W2_q_b[4]_PORT_A_write_enable_reg, W2_q_b[4]_PORT_B_read_enable_reg, , , W2_q_b[4]_clock_0, W2_q_b[4]_clock_1, , , , );
W2_q_b[4] = W2_q_b[4]_PORT_B_data_out[0];

--W2_q_b[1] is dram:inst14|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|q_b[1] at M4K_X13_Y7
W2_q_b[4]_PORT_A_data_in = BUS(T2_data[4], T2_data[1]);
W2_q_b[4]_PORT_A_data_in_reg = DFFE(W2_q_b[4]_PORT_A_data_in, W2_q_b[4]_clock_0, , , );
W2_q_b[4]_PORT_A_address = BUS(T2_cnt2[0], T2_cnt2[1], T2_cnt2[2], T2_cnt2[3], T2_cnt2[4], T2_cnt2[5], T2_cnt2[6], T2_cnt2[7], T2_cnt2[8], T2_cnt2[9], T2_cnt2[10]);
W2_q_b[4]_PORT_A_address_reg = DFFE(W2_q_b[4]_PORT_A_address, W2_q_b[4]_clock_0, , , );
W2_q_b[4]_PORT_B_address = BUS(L1_COUNTER[0], L1_COUNTER[1], L1_COUNTER[2], L1_COUNTER[3], L1_COUNTER[4], L1_COUNTER[5], L1_COUNTER[6], L1_COUNTER[7], L1_COUNTER[8], L1_COUNTER[9], L1_COUNTER[10]);
W2_q_b[4]_PORT_B_address_reg = DFFE(W2_q_b[4]_PORT_B_address, W2_q_b[4]_clock_1, , , );
W2_q_b[4]_PORT_A_write_enable = VCC;
W2_q_b[4]_PORT_A_write_enable_reg = DFFE(W2_q_b[4]_PORT_A_write_enable, W2_q_b[4]_clock_0, , , );
W2_q_b[4]_PORT_B_read_enable = VCC;
W2_q_b[4]_PORT_B_read_enable_reg = DFFE(W2_q_b[4]_PORT_B_read_enable, W2_q_b[4]_clock_1, , , );
W2_q_b[4]_clock_0 = GLOBAL(CLK);
W2_q_b[4]_clock_1 = GLOBAL(CLK);
W2_q_b[4]_PORT_B_data_out = MEMORY(W2_q_b[4]_PORT_A_data_in_reg, , W2_q_b[4]_PORT_A_address_reg, W2_q_b[4]_PORT_B_address_reg, W2_q_b[4]_PORT_A_write_enable_reg, W2_q_b[4]_PORT_B_read_enable_reg, , , W2_q_b[4]_clock_0, W2_q_b[4]_clock_1, , , , );
W2_q_b[1] = W2_q_b[4]_PORT_B_data_out[1];


--G1_RAMTMP5[4] is BUS_1:inst5|RAMTMP5[4] at LC_X11_Y5_N0
--operation mode is normal

G1_RAMTMP5[4]_lut_out = Y1_q_a[5] & (G1_RAMTMP5[4] # G1L69 & A1L54) # !Y1_q_a[5] & G1L69 & A1L54;
G1_RAMTMP5[4] = DFFEA(G1_RAMTMP5[4]_lut_out, !GLOBAL(CLK), VCC, , G1L92, , );


--G1_RAMTMP2[4] is BUS_1:inst5|RAMTMP2[4] at LC_X17_Y5_N5
--operation mode is normal

G1_RAMTMP2[4]_lut_out = Y1_q_a[6] & (G1_RAMTMP2[4] # G1L59 & A1L54) # !Y1_q_a[6] & G1L59 & A1L54;
G1_RAMTMP2[4] = DFFEA(G1_RAMTMP2[4]_lut_out, !GLOBAL(CLK), VCC, , G1L92, , );


--W2_q_b[3] is dram:inst14|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|q_b[3] at M4K_X13_Y10
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 2048, Port A Width: 2, Port B Depth: 2048, Port B Width: 2
--Port A Logical Depth: 2048, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
W2_q_b[3]_PORT_A_data_in = BUS(T2_data[3], T2_data[0]);
W2_q_b[3]_PORT_A_data_in_reg = DFFE(W2_q_b[3]_PORT_A_data_in, W2_q_b[3]_clock_0, , , );
W2_q_b[3]_PORT_A_address = BUS(T2_cnt2[0], T2_cnt2[1], T2_cnt2[2], T2_cnt2[3], T2_cnt2[4], T2_cnt2[5], T2_cnt2[6], T2_cnt2[7], T2_cnt2[8], T2_cnt2[9], T2_cnt2[10]);
W2_q_b[3]_PORT_A_address_reg = DFFE(W2_q_b[3]_PORT_A_address, W2_q_b[3]_clock_0, , , );
W2_q_b[3]_PORT_B_address = BUS(L1_COUNTER[0], L1_COUNTER[1], L1_COUNTER[2], L1_COUNTER[3], L1_COUNTER[4], L1_COUNTER[5], L1_COUNTER[6], L1_COUNTER[7], L1_COUNTER[8], L1_COUNTER[9], L1_COUNTER[10]);
W2_q_b[3]_PORT_B_address_reg = DFFE(W2_q_b[3]_PORT_B_address, W2_q_b[3]_clock_1, , , );
W2_q_b[3]_PORT_A_write_enable = VCC;
W2_q_b[3]_PORT_A_write_enable_reg = DFFE(W2_q_b[3]_PORT_A_write_enable, W2_q_b[3]_clock_0, , , );
W2_q_b[3]_PORT_B_read_enable = VCC;
W2_q_b[3]_PORT_B_read_enable_reg = DFFE(W2_q_b[3]_PORT_B_read_enable, W2_q_b[3]_clock_1, , , );
W2_q_b[3]_clock_0 = GLOBAL(CLK);
W2_q_b[3]_clock_1 = GLOBAL(CLK);
W2_q_b[3]_PORT_B_data_out = MEMORY(W2_q_b[3]_PORT_A_data_in_reg, , W2_q_b[3]_PORT_A_address_reg, W2_q_b[3]_PORT_B_address_reg, W2_q_b[3]_PORT_A_write_enable_reg, W2_q_b[3]_PORT_B_read_enable_reg, , , W2_q_b[3]_clock_0, W2_q_b[3]_clock_1, , , , );
W2_q_b[3] = W2_q_b[3]_PORT_B_data_out[0];

--W2_q_b[0] is dram:inst14|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|q_b[0] at M4K_X13_Y10
W2_q_b[3]_PORT_A_data_in = BUS(T2_data[3], T2_data[0]);
W2_q_b[3]_PORT_A_data_in_reg = DFFE(W2_q_b[3]_PORT_A_data_in, W2_q_b[3]_clock_0, , , );
W2_q_b[3]_PORT_A_address = BUS(T2_cnt2[0], T2_cnt2[1], T2_cnt2[2], T2_cnt2[3], T2_cnt2[4], T2_cnt2[5], T2_cnt2[6], T2_cnt2[7], T2_cnt2[8], T2_cnt2[9], T2_cnt2[10]);
W2_q_b[3]_PORT_A_address_reg = DFFE(W2_q_b[3]_PORT_A_address, W2_q_b[3]_clock_0, , , );
W2_q_b[3]_PORT_B_address = BUS(L1_COUNTER[0], L1_COUNTER[1], L1_COUNTER[2], L1_COUNTER[3], L1_COUNTER[4], L1_COUNTER[5], L1_COUNTER[6], L1_COUNTER[7], L1_COUNTER[8], L1_COUNTER[9], L1_COUNTER[10]);
W2_q_b[3]_PORT_B_address_reg = DFFE(W2_q_b[3]_PORT_B_address, W2_q_b[3]_clock_1, , , );
W2_q_b[3]_PORT_A_write_enable = VCC;
W2_q_b[3]_PORT_A_write_enable_reg = DFFE(W2_q_b[3]_PORT_A_write_enable, W2_q_b[3]_clock_0, , , );
W2_q_b[3]_PORT_B_read_enable = VCC;
W2_q_b[3]_PORT_B_read_enable_reg = DFFE(W2_q_b[3]_PORT_B_read_enable, W2_q_b[3]_clock_1, , , );
W2_q_b[3]_clock_0 = GLOBAL(CLK);
W2_q_b[3]_clock_1 = GLOBAL(CLK);
W2_q_b[3]_PORT_B_data_out = MEMORY(W2_q_b[3]_PORT_A_data_in_reg, , W2_q_b[3]_PORT_A_address_reg, W2_q_b[3]_PORT_B_address_reg, W2_q_b[3]_PORT_A_write_enable_reg, W2_q_b[3]_PORT_B_read_enable_reg, , , W2_q_b[3]_clock_0, W2_q_b[3]_clock_1, , , , );
W2_q_b[0] = W2_q_b[3]_PORT_B_data_out[1];


--G1_RAMTMP5[3] is BUS_1:inst5|RAMTMP5[3] at LC_X10_Y4_N0
--operation mode is normal

G1_RAMTMP5[3]_lut_out = G1L69 & (A1L64 # Y1_q_a[5] & G1_RAMTMP5[3]) # !G1L69 & Y1_q_a[5] & G1_RAMTMP5[3];
G1_RAMTMP5[3] = DFFEA(G1_RAMTMP5[3]_lut_out, !GLOBAL(CLK), VCC, , G1L92, , );


--W1_q_b[3] is dram:inst|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|q_b[3] at M4K_X13_Y4
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 2048, Port A Width: 2, Port B Depth: 2048, Port B Width: 2
--Port A Logical Depth: 2048, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
W1_q_b[3]_PORT_A_data_in = BUS(T1_data[3], T1_data[2]);
W1_q_b[3]_PORT_A_data_in_reg = DFFE(W1_q_b[3]_PORT_A_data_in, W1_q_b[3]_clock_0, , , );
W1_q_b[3]_PORT_A_address = BUS(T1_cnt2[0], T1_cnt2[1], T1_cnt2[2], T1_cnt2[3], T1_cnt2[4], T1_cnt2[5], T1_cnt2[6], T1_cnt2[7], T1_cnt2[8], T1_cnt2[9], T1_cnt2[10]);
W1_q_b[3]_PORT_A_address_reg = DFFE(W1_q_b[3]_PORT_A_address, W1_q_b[3]_clock_0, , , );
W1_q_b[3]_PORT_B_address = BUS(L1_COUNTER[0], L1_COUNTER[1], L1_COUNTER[2], L1_COUNTER[3], L1_COUNTER[4], L1_COUNTER[5], L1_COUNTER[6], L1_COUNTER[7], L1_COUNTER[8], L1_COUNTER[9], L1_COUNTER[10]);
W1_q_b[3]_PORT_B_address_reg = DFFE(W1_q_b[3]_PORT_B_address, W1_q_b[3]_clock_1, , , );
W1_q_b[3]_PORT_A_write_enable = VCC;
W1_q_b[3]_PORT_A_write_enable_reg = DFFE(W1_q_b[3]_PORT_A_write_enable, W1_q_b[3]_clock_0, , , );
W1_q_b[3]_PORT_B_read_enable = VCC;
W1_q_b[3]_PORT_B_read_enable_reg = DFFE(W1_q_b[3]_PORT_B_read_enable, W1_q_b[3]_clock_1, , , );
W1_q_b[3]_clock_0 = GLOBAL(CLK);
W1_q_b[3]_clock_1 = GLOBAL(CLK);
W1_q_b[3]_PORT_B_data_out = MEMORY(W1_q_b[3]_PORT_A_data_in_reg, , W1_q_b[3]_PORT_A_address_reg, W1_q_b[3]_PORT_B_address_reg, W1_q_b[3]_PORT_A_write_enable_reg, W1_q_b[3]_PORT_B_read_enable_reg, , , W1_q_b[3]_clock_0, W1_q_b[3]_clock_1, , , , );
W1_q_b[3] = W1_q_b[3]_PORT_B_data_out[0];

--W1_q_b[2] is dram:inst|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|q_b[2] at M4K_X13_Y4
W1_q_b[3]_PORT_A_data_in = BUS(T1_data[3], T1_data[2]);
W1_q_b[3]_PORT_A_data_in_reg = DFFE(W1_q_b[3]_PORT_A_data_in, W1_q_b[3]_clock_0, , , );
W1_q_b[3]_PORT_A_address = BUS(T1_cnt2[0], T1_cnt2[1], T1_cnt2[2], T1_cnt2[3], T1_cnt2[4], T1_cnt2[5], T1_cnt2[6], T1_cnt2[7], T1_cnt2[8], T1_cnt2[9], T1_cnt2[10]);
W1_q_b[3]_PORT_A_address_reg = DFFE(W1_q_b[3]_PORT_A_address, W1_q_b[3]_clock_0, , , );
W1_q_b[3]_PORT_B_address = BUS(L1_COUNTER[0], L1_COUNTER[1], L1_COUNTER[2], L1_COUNTER[3], L1_COUNTER[4], L1_COUNTER[5], L1_COUNTER[6], L1_COUNTER[7], L1_COUNTER[8], L1_COUNTER[9], L1_COUNTER[10]);
W1_q_b[3]_PORT_B_address_reg = DFFE(W1_q_b[3]_PORT_B_address, W1_q_b[3]_clock_1, , , );
W1_q_b[3]_PORT_A_write_enable = VCC;
W1_q_b[3]_PORT_A_write_enable_reg = DFFE(W1_q_b[3]_PORT_A_write_enable, W1_q_b[3]_clock_0, , , );
W1_q_b[3]_PORT_B_read_enable = VCC;
W1_q_b[3]_PORT_B_read_enable_reg = DFFE(W1_q_b[3]_PORT_B_read_enable, W1_q_b[3]_clock_1, , , );
W1_q_b[3]_clock_0 = GLOBAL(CLK);
W1_q_b[3]_clock_1 = GLOBAL(CLK);
W1_q_b[3]_PORT_B_data_out = MEMORY(W1_q_b[3]_PORT_A_data_in_reg, , W1_q_b[3]_PORT_A_address_reg, W1_q_b[3]_PORT_B_address_reg, W1_q_b[3]_PORT_A_write_enable_reg, W1_q_b[3]_PORT_B_read_enable_reg, , , W1_q_b[3]_clock_0, W1_q_b[3]_clock_1, , , , );
W1_q_b[2] = W1_q_b[3]_PORT_B_data_out[1];


--G1_RAMTMP2[3] is BUS_1:inst5|RAMTMP2[3] at LC_X17_Y5_N4
--operation mode is normal

G1_RAMTMP2[3]_lut_out = A1L64 & (G1L59 # G1_RAMTMP2[3] & Y1_q_a[6]) # !A1L64 & G1_RAMTMP2[3] & Y1_q_a[6];
G1_RAMTMP2[3] = DFFEA(G1_RAMTMP2[3]_lut_out, !GLOBAL(CLK), VCC, , G1L92, , );


--G1_RAMTMP5[2] is BUS_1:inst5|RAMTMP5[2] at LC_X10_Y4_N2
--operation mode is normal

G1_RAMTMP5[2]_lut_out = Y1_q_a[5] & (G1_RAMTMP5[2] # A1L74 & G1L69) # !Y1_q_a[5] & A1L74 & G1L69;
G1_RAMTMP5[2] = DFFEA(G1_RAMTMP5[2]_lut_out, !GLOBAL(CLK), VCC, , G1L92, , );


--G1_RAMTMP2[2] is BUS_1:inst5|RAMTMP2[2] at LC_X17_Y5_N2
--operation mode is normal

G1_RAMTMP2[2]_lut_out = Y1_q_a[6] & (G1_RAMTMP2[2] # G1L59 & A1L74) # !Y1_q_a[6] & G1L59 & A1L74;
G1_RAMTMP2[2] = DFFEA(G1_RAMTMP2[2]_lut_out, !GLOBAL(CLK), VCC, , G1L92, , );


--G1_RAMTMP5[1] is BUS_1:inst5|RAMTMP5[1] at LC_X10_Y7_N8
--operation mode is normal

G1_RAMTMP5[1]_lut_out = G1L69 & (A1L84 # G1_RAMTMP5[1] & Y1_q_a[5]) # !G1L69 & G1_RAMTMP5[1] & Y1_q_a[5];
G1_RAMTMP5[1] = DFFEA(G1_RAMTMP5[1]_lut_out, !GLOBAL(CLK), VCC, , G1L92, , );


--W1_q_b[1] is dram:inst|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|q_b[1] at M4K_X13_Y5
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 2048, Port A Width: 2, Port B Depth: 2048, Port B Width: 2
--Port A Logical Depth: 2048, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
W1_q_b[1]_PORT_A_data_in = BUS(T1_data[1], T1_data[0]);
W1_q_b[1]_PORT_A_data_in_reg = DFFE(W1_q_b[1]_PORT_A_data_in, W1_q_b[1]_clock_0, , , );
W1_q_b[1]_PORT_A_address = BUS(T1_cnt2[0], T1_cnt2[1], T1_cnt2[2], T1_cnt2[3], T1_cnt2[4], T1_cnt2[5], T1_cnt2[6], T1_cnt2[7], T1_cnt2[8], T1_cnt2[9], T1_cnt2[10]);
W1_q_b[1]_PORT_A_address_reg = DFFE(W1_q_b[1]_PORT_A_address, W1_q_b[1]_clock_0, , , );
W1_q_b[1]_PORT_B_address = BUS(L1_COUNTER[0], L1_COUNTER[1], L1_COUNTER[2], L1_COUNTER[3], L1_COUNTER[4], L1_COUNTER[5], L1_COUNTER[6], L1_COUNTER[7], L1_COUNTER[8], L1_COUNTER[9], L1_COUNTER[10]);
W1_q_b[1]_PORT_B_address_reg = DFFE(W1_q_b[1]_PORT_B_address, W1_q_b[1]_clock_1, , , );
W1_q_b[1]_PORT_A_write_enable = VCC;
W1_q_b[1]_PORT_A_write_enable_reg = DFFE(W1_q_b[1]_PORT_A_write_enable, W1_q_b[1]_clock_0, , , );
W1_q_b[1]_PORT_B_read_enable = VCC;
W1_q_b[1]_PORT_B_read_enable_reg = DFFE(W1_q_b[1]_PORT_B_read_enable, W1_q_b[1]_clock_1, , , );
W1_q_b[1]_clock_0 = GLOBAL(CLK);
W1_q_b[1]_clock_1 = GLOBAL(CLK);
W1_q_b[1]_PORT_B_data_out = MEMORY(W1_q_b[1]_PORT_A_data_in_reg, , W1_q_b[1]_PORT_A_address_reg, W1_q_b[1]_PORT_B_address_reg, W1_q_b[1]_PORT_A_write_enable_reg, W1_q_b[1]_PORT_B_read_enable_reg, , , W1_q_b[1]_clock_0, W1_q_b[1]_clock_1, , , , );
W1_q_b[1] = W1_q_b[1]_PORT_B_data_out[0];

--W1_q_b[0] is dram:inst|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|q_b[0] at M4K_X13_Y5
W1_q_b[1]_PORT_A_data_in = BUS(T1_data[1], T1_data[0]);
W1_q_b[1]_PORT_A_data_in_reg = DFFE(W1_q_b[1]_PORT_A_data_in, W1_q_b[1]_clock_0, , , );
W1_q_b[1]_PORT_A_address = BUS(T1_cnt2[0], T1_cnt2[1], T1_cnt2[2], T1_cnt2[3], T1_cnt2[4], T1_cnt2[5], T1_cnt2[6], T1_cnt2[7], T1_cnt2[8], T1_cnt2[9], T1_cnt2[10]);
W1_q_b[1]_PORT_A_address_reg = DFFE(W1_q_b[1]_PORT_A_address, W1_q_b[1]_clock_0, , , );
W1_q_b[1]_PORT_B_address = BUS(L1_COUNTER[0], L1_COUNTER[1], L1_COUNTER[2], L1_COUNTER[3], L1_COUNTER[4], L1_COUNTER[5], L1_COUNTER[6], L1_COUNTER[7], L1_COUNTER[8], L1_COUNTER[9], L1_COUNTER[10]);
W1_