wave.fit.eqn

数字示波器的FPGA实现 VHDL编写 Quartus7.1测试通过

N1L05 = CARRY(N1L05_cout_1);


--N2L1 is VOLTAGE_CONV:inst15|add~1 at LC_X17_Y6_N0
--operation mode is arithmetic

N2L1 = G1_RAMTMP2[0] $ W1_q_b[0];

--N2_TEMP[0] is VOLTAGE_CONV:inst15|TEMP[0] at LC_X17_Y6_N0
--operation mode is arithmetic

N2_TEMP[0] = DFFEA(N2L1, !GLOBAL(P1_CLK), !GLOBAL(U1L6), , !N2L64, , );

--N2L94 is VOLTAGE_CONV:inst15|TEMP[0]~COUT0 at LC_X17_Y6_N0
--operation mode is arithmetic

N2L94_cout_0 = G1_RAMTMP2[0] & W1_q_b[0];
N2L94 = CARRY(N2L94_cout_0);

--N2L05 is VOLTAGE_CONV:inst15|TEMP[0]~COUT1 at LC_X17_Y6_N0
--operation mode is arithmetic

N2L05_cout_1 = G1_RAMTMP2[0] & W1_q_b[0];
N2L05 = CARRY(N2L05_cout_1);


--F1_REG_Q[14] is generator_accB:inst4|REG_Q[14] at LC_X16_Y9_N5
--operation mode is normal

F1_REG_Q[14]_lut_out = F1L15 & (F1L99 # !F1L57 # !F1L37);
F1_REG_Q[14] = DFFEA(F1_REG_Q[14]_lut_out, GLOBAL(K1_CLK), !G1_TMP, , , , );


--F1_REG_Q[13] is generator_accB:inst4|REG_Q[13] at LC_X16_Y9_N9
--operation mode is normal

F1_REG_Q[13]_lut_out = F1L74 & (F1L99 # !F1L57 # !F1L37);
F1_REG_Q[13] = DFFEA(F1_REG_Q[13]_lut_out, GLOBAL(K1_CLK), !G1_TMP, , , , );


--F1_REG_Q[12] is generator_accB:inst4|REG_Q[12] at LC_X16_Y9_N7
--operation mode is normal

F1_REG_Q[12]_lut_out = F1L34 & (F1L99 # !F1L57 # !F1L37);
F1_REG_Q[12] = DFFEA(F1_REG_Q[12]_lut_out, GLOBAL(K1_CLK), !G1_TMP, , , , );


--G1_P0_OUT[7] is BUS_1:inst5|P0_OUT[7] at LC_X20_Y3_N4
--operation mode is normal

G1_P0_OUT[7]_lut_out = H1_TEMP[15] & (G1L02 # !G1L29) # !H1_TEMP[15] & G1L29 & G1L02;
G1_P0_OUT[7]_sload_eqn = (G1L19 & H1_TEMP[7]) # (!G1L19 & G1_P0_OUT[7]_lut_out);
G1_P0_OUT[7] = DFFEA(G1_P0_OUT[7]_sload_eqn, GLOBAL(CLK), VCC, , G1L82, , );


--G1_GX is BUS_1:inst5|GX at LC_X22_Y4_N7
--operation mode is normal

G1_GX_lut_out = G1L82 & (G1L19 # !G1L39 # !G1L29);
G1_GX = DFFEA(G1_GX_lut_out, GLOBAL(CLK), VCC, , , , );


--G1_P0_OUT[6] is BUS_1:inst5|P0_OUT[6] at LC_X22_Y4_N2
--operation mode is normal

G1_P0_OUT[6]_lut_out = G1L29 & G1L12 # !G1L29 & H1_TEMP[14];
G1_P0_OUT[6]_sload_eqn = (G1L19 & H1_TEMP[6]) # (!G1L19 & G1_P0_OUT[6]_lut_out);
G1_P0_OUT[6] = DFFEA(G1_P0_OUT[6]_sload_eqn, GLOBAL(CLK), VCC, , G1L82, , );


--G1_P0_OUT[5] is BUS_1:inst5|P0_OUT[5] at LC_X22_Y4_N4
--operation mode is normal

G1_P0_OUT[5]_lut_out = G1L29 & G1L22 # !G1L29 & H1_TEMP[13];
G1_P0_OUT[5]_sload_eqn = (G1L19 & H1_TEMP[5]) # (!G1L19 & G1_P0_OUT[5]_lut_out);
G1_P0_OUT[5] = DFFEA(G1_P0_OUT[5]_sload_eqn, GLOBAL(CLK), VCC, , G1L82, , );


--G1_P0_OUT[4] is BUS_1:inst5|P0_OUT[4] at LC_X22_Y4_N9
--operation mode is normal

G1_P0_OUT[4]_lut_out = G1L29 & G1L32 # !G1L29 & H1_TEMP[12];
G1_P0_OUT[4]_sload_eqn = (G1L19 & H1_TEMP[4]) # (!G1L19 & G1_P0_OUT[4]_lut_out);
G1_P0_OUT[4] = DFFEA(G1_P0_OUT[4]_sload_eqn, GLOBAL(CLK), VCC, , G1L82, , );


--G1_P0_OUT[3] is BUS_1:inst5|P0_OUT[3] at LC_X22_Y5_N9
--operation mode is normal

G1_P0_OUT[3]_lut_out = G1L29 & G1L42 # !G1L29 & H1_TEMP[11];
G1_P0_OUT[3]_sload_eqn = (G1L19 & H1_TEMP[3]) # (!G1L19 & G1_P0_OUT[3]_lut_out);
G1_P0_OUT[3] = DFFEA(G1_P0_OUT[3]_sload_eqn, GLOBAL(CLK), VCC, , G1L82, , );


--G1_P0_OUT[2] is BUS_1:inst5|P0_OUT[2] at LC_X22_Y5_N5
--operation mode is normal

G1_P0_OUT[2]_lut_out = G1L29 & G1L52 # !G1L29 & H1_TEMP[10];
G1_P0_OUT[2]_sload_eqn = (G1L19 & H1_TEMP[2]) # (!G1L19 & G1_P0_OUT[2]_lut_out);
G1_P0_OUT[2] = DFFEA(G1_P0_OUT[2]_sload_eqn, GLOBAL(CLK), VCC, , G1L82, , );


--G1_P0_OUT[1] is BUS_1:inst5|P0_OUT[1] at LC_X22_Y4_N3
--operation mode is normal

G1_P0_OUT[1]_lut_out = G1L29 & G1L62 # !G1L29 & H1_TEMP[9];
G1_P0_OUT[1]_sload_eqn = (G1L19 & H1_TEMP[1]) # (!G1L19 & G1_P0_OUT[1]_lut_out);
G1_P0_OUT[1] = DFFEA(G1_P0_OUT[1]_sload_eqn, GLOBAL(CLK), VCC, , G1L82, , );


--G1_P0_OUT[0] is BUS_1:inst5|P0_OUT[0] at LC_X22_Y5_N4
--operation mode is normal

G1_P0_OUT[0]_lut_out = G1L29 & G1L72 # !G1L29 & H1_TEMP[8];
G1_P0_OUT[0]_sload_eqn = (G1L19 & H1_TEMP[0]) # (!G1L19 & G1_P0_OUT[0]_lut_out);
G1_P0_OUT[0] = DFFEA(G1_P0_OUT[0]_sload_eqn, GLOBAL(CLK), VCC, , G1L82, , );


--W2_q_b[7] is dram:inst14|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|q_b[7] at M4K_X13_Y8
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 2048, Port A Width: 2, Port B Depth: 2048, Port B Width: 2
--Port A Logical Depth: 2048, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
W2_q_b[7]_PORT_A_data_in = BUS(T2_data[7], T2_data[2]);
W2_q_b[7]_PORT_A_data_in_reg = DFFE(W2_q_b[7]_PORT_A_data_in, W2_q_b[7]_clock_0, , , );
W2_q_b[7]_PORT_A_address = BUS(T2_cnt2[0], T2_cnt2[1], T2_cnt2[2], T2_cnt2[3], T2_cnt2[4], T2_cnt2[5], T2_cnt2[6], T2_cnt2[7], T2_cnt2[8], T2_cnt2[9], T2_cnt2[10]);
W2_q_b[7]_PORT_A_address_reg = DFFE(W2_q_b[7]_PORT_A_address, W2_q_b[7]_clock_0, , , );
W2_q_b[7]_PORT_B_address = BUS(L1_COUNTER[0], L1_COUNTER[1], L1_COUNTER[2], L1_COUNTER[3], L1_COUNTER[4], L1_COUNTER[5], L1_COUNTER[6], L1_COUNTER[7], L1_COUNTER[8], L1_COUNTER[9], L1_COUNTER[10]);
W2_q_b[7]_PORT_B_address_reg = DFFE(W2_q_b[7]_PORT_B_address, W2_q_b[7]_clock_1, , , );
W2_q_b[7]_PORT_A_write_enable = VCC;
W2_q_b[7]_PORT_A_write_enable_reg = DFFE(W2_q_b[7]_PORT_A_write_enable, W2_q_b[7]_clock_0, , , );
W2_q_b[7]_PORT_B_read_enable = VCC;
W2_q_b[7]_PORT_B_read_enable_reg = DFFE(W2_q_b[7]_PORT_B_read_enable, W2_q_b[7]_clock_1, , , );
W2_q_b[7]_clock_0 = GLOBAL(CLK);
W2_q_b[7]_clock_1 = GLOBAL(CLK);
W2_q_b[7]_PORT_B_data_out = MEMORY(W2_q_b[7]_PORT_A_data_in_reg, , W2_q_b[7]_PORT_A_address_reg, W2_q_b[7]_PORT_B_address_reg, W2_q_b[7]_PORT_A_write_enable_reg, W2_q_b[7]_PORT_B_read_enable_reg, , , W2_q_b[7]_clock_0, W2_q_b[7]_clock_1, , , , );
W2_q_b[7] = W2_q_b[7]_PORT_B_data_out[0];

--W2_q_b[2] is dram:inst14|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|q_b[2] at M4K_X13_Y8
W2_q_b[7]_PORT_A_data_in = BUS(T2_data[7], T2_data[2]);
W2_q_b[7]_PORT_A_data_in_reg = DFFE(W2_q_b[7]_PORT_A_data_in, W2_q_b[7]_clock_0, , , );
W2_q_b[7]_PORT_A_address = BUS(T2_cnt2[0], T2_cnt2[1], T2_cnt2[2], T2_cnt2[3], T2_cnt2[4], T2_cnt2[5], T2_cnt2[6], T2_cnt2[7], T2_cnt2[8], T2_cnt2[9], T2_cnt2[10]);
W2_q_b[7]_PORT_A_address_reg = DFFE(W2_q_b[7]_PORT_A_address, W2_q_b[7]_clock_0, , , );
W2_q_b[7]_PORT_B_address = BUS(L1_COUNTER[0], L1_COUNTER[1], L1_COUNTER[2], L1_COUNTER[3], L1_COUNTER[4], L1_COUNTER[5], L1_COUNTER[6], L1_COUNTER[7], L1_COUNTER[8], L1_COUNTER[9], L1_COUNTER[10]);
W2_q_b[7]_PORT_B_address_reg = DFFE(W2_q_b[7]_PORT_B_address, W2_q_b[7]_clock_1, , , );
W2_q_b[7]_PORT_A_write_enable = VCC;
W2_q_b[7]_PORT_A_write_enable_reg = DFFE(W2_q_b[7]_PORT_A_write_enable, W2_q_b[7]_clock_0, , , );
W2_q_b[7]_PORT_B_read_enable = VCC;
W2_q_b[7]_PORT_B_read_enable_reg = DFFE(W2_q_b[7]_PORT_B_read_enable, W2_q_b[7]_clock_1, , , );
W2_q_b[7]_clock_0 = GLOBAL(CLK);
W2_q_b[7]_clock_1 = GLOBAL(CLK);
W2_q_b[7]_PORT_B_data_out = MEMORY(W2_q_b[7]_PORT_A_data_in_reg, , W2_q_b[7]_PORT_A_address_reg, W2_q_b[7]_PORT_B_address_reg, W2_q_b[7]_PORT_A_write_enable_reg, W2_q_b[7]_PORT_B_read_enable_reg, , , W2_q_b[7]_clock_0, W2_q_b[7]_clock_1, , , , );
W2_q_b[2] = W2_q_b[7]_PORT_B_data_out[1];


--G1_RAMTMP5[7] is BUS_1:inst5|RAMTMP5[7] at LC_X10_Y4_N4
--operation mode is normal

G1_RAMTMP5[7]_lut_out = G1L69 & (A1L24 # G1_RAMTMP5[7] & Y1_q_a[5]) # !G1L69 & G1_RAMTMP5[7] & Y1_q_a[5];
G1_RAMTMP5[7] = DFFEA(G1_RAMTMP5[7]_lut_out, !GLOBAL(CLK), VCC, , G1L92, , );


--U1L2Q is CONV_SINGLE:inst22|CURRENT_STATE~11 at LC_X8_Y5_N0
--operation mode is normal

U1L2Q_lut_out = G1_RAMTMP6[0] & (U1L2Q & U1L27 # !U1L1Q);
U1L2Q = DFFEA(U1L2Q_lut_out, GLOBAL(CLK), VCC, , , , );


--U1L4Q is CONV_SINGLE:inst22|CURRENT_STATE~13 at LC_X10_Y5_N9
--operation mode is normal

U1L4Q_lut_out = U1L4Q & (U1L66 # U1L73 & U1L3Q) # !U1L4Q & U1L73 & U1L3Q;
U1L4Q = DFFEA(U1L4Q_lut_out, GLOBAL(CLK), VCC, , , , );


--U1L1Q is CONV_SINGLE:inst22|CURRENT_STATE~10 at LC_X8_Y5_N4
--operation mode is normal

U1L1Q_lut_out = !U1L76 & (G1_RAMTMP6[0] # !U1L27 # !U1L2Q);
U1L1Q = DFFEA(U1L1Q_lut_out, GLOBAL(CLK), VCC, , , , );


--U1L5Q is CONV_SINGLE:inst22|CURRENT_STATE~14 at LC_X10_Y5_N8
--operation mode is normal

U1L5Q_lut_out = U1L4Q & (U1L5Q & G1_RAMTMP6[0] # !U1L66) # !U1L4Q & U1L5Q & G1_RAMTMP6[0];
U1L5Q = DFFEA(U1L5Q_lut_out, GLOBAL(CLK), VCC, , , , );


--U1L7 is CONV_SINGLE:inst22|EN~78 at LC_X8_Y5_N8
--operation mode is normal

U1L7 = U1L1Q & !U1L5Q;


--U1L6 is CONV_SINGLE:inst22|EN~77 at LC_X8_Y5_N9
--operation mode is normal

U1L6 = LCELL(U1L7 & (U1L6 # U1L2Q # U1L4Q));


--N1L44 is VOLTAGE_CONV:inst12|LessThan~7COUT0 at LC_X9_Y7_N6
--operation mode is arithmetic

N1L44_cout_0 = N1L51 & W2_q_b[6] & !N1L04 # !N1L51 & (W2_q_b[6] # !N1L04);
N1L44 = CARRY(N1L44_cout_0);

--N1L54 is VOLTAGE_CONV:inst12|LessThan~7COUT1 at LC_X9_Y7_N6
--operation mode is arithmetic

N1L54_cout_1 = N1L51 & W2_q_b[6] & !N1L14 # !N1L51 & (W2_q_b[6] # !N1L14);
N1L54 = CARRY(N1L54_cout_1);


--W1_q_b[7] is dram:inst|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|q_b[7] at M4K_X13_Y3
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 2048, Port A Width: 2, Port B Depth: 2048, Port B Width: 2
--Port A Logical Depth: 2048, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
W1_q_b[7]_PORT_A_data_in = BUS(T1_data[7], T1_data[5]);
W1_q_b[7]_PORT_A_data_in_reg = DFFE(W1_q_b[7]_PORT_A_data_in, W1_q_b[7]_clock_0, , , );
W1_q_b[7]_PORT_A_address = BUS(T1_cnt2[0], T1_cnt2[1], T1_cnt2[2], T1_cnt2[3], T1_cnt2[4], T1_cnt2[5], T1_cnt2[6], T1_cnt2[7], T1_cnt2[8], T1_cnt2[9], T1_cnt2[10]);
W1_q_b[7]_PORT_A_address_reg = DFFE(W1_q_b[7]_PORT_A_address, W1_q_b[7]_clock_0, , , );
W1_q_b[7]_PORT_B_address = BUS(L1_COUNTER[0], L1_COUNTER[1], L1_COUNTER[2], L1_COUNTER[3], L1_COUNTER[4], L1_COUNTER[5], L1_COUNTER[6], L1_COUNTER[7], L1_COUNTER[8], L1_COUNTER[9], L1_COUNTER[10]);
W1_q_b[7]_PORT_B_address_reg = DFFE(W1_q_b[7]_PORT_B_address, W1_q_b[7]_clock_1, , , );
W1_q_b[7]_PORT_A_write_enable = VCC;
W1_q_b[7]_PORT_A_write_enable_reg = DFFE(W1_q_b[7]_PORT_A_write_enable, W1_q_b[7]_clock_0, , , );
W1_q_b[7]_PORT_B_read_enable = VCC;
W1_q_b[7]_PORT_B_read_enable_reg = DFFE(W1_q_b[7]_PORT_B_read_enable, W1_q_b[7]_clock_1, , , );
W1_q_b[7]_clock_0 = GLOBAL(CLK);
W1_q_b[7]_clock_1 = GLOBAL(CLK);
W1_q_b[7]_PORT_B_data_out = MEMORY(W1_q_b[7]_PORT_A_data_in_reg, , W1_q_b[7]_PORT_A_address_reg, W1_q_b[7]_PORT_B_address_reg, W1_q_b[7]_PORT_A_write_enable_reg, W1_q_b[7]_PORT_B_read_enable_reg, , , W1_q_b[7]_clock_0, W1_q_b[7]_clock_1, , , , );
W1_q_b[7] = W1_q_b[7]_PORT_B_data_out[0];

--W1_q_b[5] is dram:inst|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|q_b[5] at M4K_X13_Y3
W1_q_b[7]_PORT_A_data_in = BUS(T1_data[7], T1_data[5]);
W1_q_b[7]_PORT_A_data_in_reg = DFFE(W1_q_b[7]_PORT_A_data_in, W1_q_b[7]_clock_0, , , );
W1_q_b[7]_PORT_A_address = BUS(T1_cnt2[0], T1_cnt2[1], T1_cnt2[2], T1_cnt2[3], T1_cnt2[4], T1_cnt2[5], T1_cnt2[6], T1_cnt2[7], T1_cnt2[8], T1_cnt2[9], T1_cnt2[10]);
W1_q_b[7]_PORT_A_address_reg = DFFE(W1_q_b[7]_PORT_A_address, W1_q_b[7]_clock_0, , , );
W1_q_b[7]_PORT_B_address = BUS(L1_COUNTER[0], L1_COUNTER[1], L1_COUNTER[2], L1_COUNTER[3], L1_COUNTER[4], L1_COUNTER[5], L1_COUNTER[6], L1_COUNTER[7], L1_COUNTER[8], L1_COUNTER[9], L1_COUNTER[10]);
W1_q_b[7]_PORT_B_address_reg = DFFE(W1_q_b[7]_PORT_B_address, W1_q_b[7]_clock_1, , , );
W1_q_b[7]_PORT_A_write_enable = VCC;
W1_q_b[7]_PORT_A_write_enable_reg = DFFE(W1_q_b[7]_PORT_A_write_enable, W1_q_b[7]_clock_0, , , );
W1_q_b[7]_PORT_B_read_enable = VCC;
W1_q_b[7]_PORT_B_read_enable_reg = DFFE(W1_q_b[7]_PORT_B_read_enable, W1_q_b[7]_clock_1, , , );
W1_q_b[7]_clock_0 = GLOBAL(CLK);
W1_q_b[7]_clock_1 = GLOBAL(CLK);
W1_q_b[7]_PORT_B_data_out = MEMORY(W1_q_b[7]_PORT_A_data_in_reg, , W1_q_b[7]_PORT_A_address_reg, W1_q_b[7]_PORT_B_address_reg, W1_q_b[7]_PORT_A_write_enable_reg, W1_q_b[7]_PORT_B_read_enable_reg, , , W1_q_b[7]_clock_0, W1_q_b[7]_clock_1, , , , );
W1_q_b[5] = W1_q_b[7]_PORT_B_data_out[1];


--G1_RAMTMP2[7] is BUS_1:inst5|RAMTMP2[7] at LC_X17_Y5_N1
--operation mode is normal

G1_RAMTMP2[7]_lut_out = Y1_q_a[6] & (G1_RAMTMP2[7] # G1L59 & A1L24) # !Y1_q_a[6] & G1L59 & A1L24;
G1_RAMTMP2[7] = DFFEA(G1_RAMTMP2[7]_lut_out, !GLOBAL(CLK), VCC, , G1L92, , );


--N2L44 is VOLTAGE_CONV:inst15|LessThan~7COUT0 at LC_X18_Y6_N6
--operation mode is arithmetic

N2L44_cout_0 = N2L51 & W1_q_b[6] & !N2L04 # !N2L51 & (W1_q_b[6] # !N2L04);
N2L44 = CARRY(N2L44_cout_0);

--N2L54 is VOLTAGE_CONV:inst15|LessThan~7COUT1 at LC_X18_Y6_N6
--operation mode is arithmetic

N2L54_cout_1 = N2L51 & W1_q_b[6] & !N2L14 # !N2L51 & (W1_q_b[6] # !N2L14);
N2L54 = CARRY(N2L54_cout_1);


--G1L101 is BUS_1:inst5|reduce_nor~172 at LC_X18_Y2_N0
--operation mode is normal

G1_LATCH_ADDRES[2]_qfbk = G1_LATCH_ADDRES[2];
G1L101 = G1_LATCH_ADDRES[3] & G1_LATCH_ADDRES[0] & G1_LATCH_ADDRES[2]_qfbk & G1L99;

--G1_LATCH_ADDRES[2] is BUS_1:inst5|LATCH_ADDRES[2] at LC_X18_Y2_N0
--operation mode is normal

G1_LATCH_ADDRES[2]_sload_eqn = A1L74;
G1_LATCH_ADDRES[2] = DFFEA(G1_LATCH_ADDRES[2]_sload_eqn, !GLOBAL(ALE), VCC, , , , );


--F1L75 is generator_accB:inst4|add~17 at LC_X16_Y5_N0
--operation mode is arithmetic

F1L75_carry_eqn = F1L65;
F1L75 = F1_REG_Q[16] $ !F1L75_carry_eqn;

--F1L95 is generator_accB:inst4|add~17COUT0 at LC_X16_Y5_N0
--operation mode is arithmetic

F1L95_cout_0 = F1_REG_Q[16] & !F1L65;
F1L95 = CARRY(F1L95_cout_0);